Classic-quantum injection interface device

ABSTRACT

Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.

REFERENCE TO PRIORITY APPLICATIONS

This application claims the benefit of U.S. Provisional Application No. 62/687,800, filed Jun. 20, 2018, entitled “Electric Signal Pulse-Width And Amplitude Controlled And Re-Programmable Semiconductor Quantum Rotation Gates,” U.S. Provisional Application No. 62/687,803, filed Jun. 21, 2018, entitled “Semiconductor Quantum Structures and Computing Circuits Using Local Depleted Well Tunneling,” U.S. Provisional Application No. 62/689,100, filed Jun. 23, 2018, entitled “Semiconductor Controlled Entangled-Aperture-Logic Quantum Shift Register,” U.S. Provisional Application No. 62/694,022, filed Jul. 5, 2018, entitled “Double-V Semiconductor Entangled-Aperture-Logic Parallel Quantum Interaction Path,” U.S. Provisional Application No. 62/687,779, filed Jun. 20, 2018, entitled “Semiconductor Quantum Structures And Gates Using Through-Thin-Oxide Well-To-Gate Aperture Tunneling,” U.S. Provisional Application No. 62/687,793, filed Jun. 20, 2018, entitled “Controlled Semiconductor Quantum Structures And Computing Circuits Using Aperture Well-To-Gate Tunneling,” U.S. Provisional Application No. 62/688,341, filed Jun. 21, 2018, entitled “3D Semiconductor Quantum Structures And Computing Circuits Using Fin-To-Gate Tunneling,” U.S. Provisional Application No. 62/689,035, filed Jun. 22, 2018, entitled “3D Semiconductor Quantum Structures And Computing Circuits Using Controlled Tunneling Through Local Fin Depletion Regions,” U.S. Provisional Application No. 62/689,291, filed Jun. 25, 2018, entitled “Semiconductor Quantum Dot And Qubit Structures Using Aperture-Tunneling Through Oxide Layer,” U.S. Provisional Application No. 62/689,166, filed Jun. 24, 2018, entitled “Semiconductor Entangled-Aperture-Logic Quantum Ancillary Gates,” U.S. Provisional Application No. 62/692,745, filed Jun. 20, 2018, entitled “Re-Programmable And Re-Configurable Quantum Processor Using Pulse-Width Based Rotation Selection And Path Access Or Bifurcation Control,” U.S. Provisional Application No. 62/692,804, filed Jul. 1, 2018, entitled “Quantum Processor With Dual-Path Quantum Error Correction,” U.S. Provisional Application No. 62/692,844, filed Jul. 1, 2018, entitled “Quantum Computing Machine With Partial Data Readout And Re-Injection Into The Quantum State,” U.S. Provisional Application No. 62/726,290, filed Jun. 20, 2018, entitled “Controlled-NOT and Tofolli Semiconductor Entangled-Aperture-Logic Quantum Gates,” U.S. Provisional Application No. 62/695,842, filed Jul. 10, 2018, entitled “Entangled Aperture-Logic Semiconductor Quantum Computing Structure with Intermediary Interactor Path,” U.S. Provisional Application No. 62/698,278, filed Jul. 15, 2018, entitled “Entangled Aperture-Logic Semiconductor Quantum Bifurcation and Merging Gate,” U.S. Provisional Application No. 62/726,397, filed Sep. 3, 2018, entitled “Semiconductor Quantum Structure With Simultaneous Shift Into Entangled State,” U.S. Provisional Application No. 62/791,818, filed Jan. 13, 2019, entitled “Semiconductor Process for Quantum Structures with Staircase Active Well,” U.S. Provisional Application No. 62/788,865, filed Jan. 6, 2018, entitled “Semiconductor Process For Quantum Structures Without Inner Contacts And Doping Layers,” U.S. Provisional Application No. 62/794,591, filed Jan. 19, 2019, entitled “Semiconductor Quantum Structures Using Localized Aperture Channel Tunneling Through Controlled Depletion Region,” U.S. Provisional Application No. 62/703,888, filed July 27, 2018, entitled “Aperture Tunneling Semiconductor Quantum Dots and Chord-Line Quantum Computing Structures,” U.S. Provisional Application No. 62/726,271, filed Sep. 2, 2018, entitled “Controlled Local Thermal Activation Of Freeze-Out Semiconductor Circuits For Cryogenic Operation,” U.S. Provisional Application No. 62/731,810, filed Sep. 14, 2018, entitled “Multi-Stage Semiconductor Quantum Detector with Anti-Correlation Merged With Quantum Core,” and U.S. Provisional Application No. 62/794,655, filed Jan. 20, 2019, entitled “Semiconductor Quantum Structures Using Preferential Tunneling Direction Through Thin Insulator Layers.” All of which are incorporated herein by reference in their entirety.

FIELD OF THE DISCLOSURE

The subject matter disclosed herein relates to the field of quantum computing and more particularly relates to planar quantum structures using tunneling through an oxide layer, tunneling through a local depleted well, and 3D quantum structures using tunneling through an oxide layer, tunneling through a local depleted fin.

BACKGROUND OF THE INVENTION

Quantum computers are machines that perform computations using the quantum effects between elementary particles, e.g., electrons, holes, ions, photons, atoms, molecules, etc. Quantum computing utilizes quantum-mechanical phenomena such as superposition and entanglement to perform computation. Quantum computing is fundamentally linked to the superposition and entanglement effects and the processing of the resulting entanglement states. A quantum computer is used to perform such computations which can be implemented theoretically or physically.

Currently, analog and digital are the two main approaches to physically implementing a quantum computer. Analog approaches are further divided into quantum simulation, quantum annealing, and adiabatic quantum computation. Digital quantum computers use quantum logic gates to do computation. Both approaches use quantum bits referred to as qubits.

Qubits are fundamental to quantum computing and are somewhat analogous to bits in a classical computer. Qubits can be in a |0> or |1> quantum state but they can also be in a superposition of the |0> and |1> states. When qubits are measured, however, they always yield a |0> or a |1> based on the quantum state they were in.

The key challenge of quantum computing is isolating such microscopic particles, loading them with the desired information, letting them interact and then preserving the result of their quantum interaction. This requires relatively good isolation from the outside world and a large suppression of the noise generated by the particle itself. Therefore, quantum structures and computers operate at very low temperatures (e.g., cryogenic), close to the absolute zero kelvin (K), in order to reduce the thermal energy/movement of the particles to well below the energy/movement coming from their desired interaction. Current physical quantum computers, however, are very noisy and quantum error correction is commonly applied to compensate for the noise.

Most existing quantum computers use superconducting structures to realize quantum interactions. Their main drawbacks, however, are the fact that superconducting structures are very large and costly and have difficulty in scaling to quantum processor sizes of thousands or millions of quantum-bits (qubits). Furthermore, they need to operate at few tens of milli-kelvin (mK) temperatures, that are difficult to achieve and where it is difficult to dissipate significant power to operate the quantum machine.

SUMMARY OF THE INVENTION

The present invention discloses several semiconductor based planar quantum structures using tunneling through an oxide layer, tunneling through a local depleted well, and 3D quantum structures using tunneling through an oxide layer, tunneling through a local depleted fin. These structures are used to construct quantum dots (qdots) and quantum bits (qubits) which are in turn used to implement quantum processor and computing circuits. Qdots, qubits, quantum gates and structures utilize semiconductor processes based on tunneling through a local depleted well. Using a continuous well with overlapping control gates allows the propagation of a quantum particle in a controlled manner from one section of the well to another. The barrier generated by the control gate either locks the particle in a certain region or allows the particle's wavefunction to partially or completely transition to another section of the well.

Interaction and entanglement between two or more particles are realized in a single continuous well or in structures consisting of a plurality of continuous wells. Multiple implementation examples adapted for a variety of semiconductor processes are disclosed and described. It is appreciated that similar principles can be applied to other processes such as nanotubes and 3D processing. Further, the quantum structure principle described herein can be applied to a variety of hybrid processes and components, including semiconductor, microelectromechanical systems (MEMS), passives, integrated passive devices (IPDs), acoustic, optical, etc.

An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.

This, additional, and/or other aspects and/or advantages of the embodiments of the present invention are set forth in the detailed description which follows; possibly inferable from the detailed description; and/or learnable by practice of the embodiments of the present invention.

There is thus provided in accordance with the invention, an interface device for interfacing between classic field effect transistor (FET) circuitry and quantum circuitry, comprising a substrate, a first substantially undoped or low-doped well constructed on said substrate in which both a classic well and a quantum well are realized, a first doped diffusion in or above said first well forming a classic well constituting a classic side of said device, a control gate constructed over at least a portion of said first well wherein a potential applied to said control gate is operative to control a tunneling path thereunder, and a second well formed by a remainder of said first well on an opposite side of said control gate forming a quantum well constituting a quantum side of said device.

There is also provided in accordance with the invention, an interface device for interfacing between classic field effect transistor (FET) circuitry and quantum circuitry, comprising a substrate, a first well constructed on said substrate and substantially doped in accordance with a classic FET device to form a classic side, a contact layer operative to establish an electric connection between a metal layer going to other classic devices and said first well, a second well constructed on said substrate and substantially undoped in accordance with a quantum structure to form a quantum side, a control gate fabricated to overlap at least a portion of said second well, and wherein application of an appropriate potential to said control gate enables tunneling of a single quantum particle through a local depleted tunneling path between said first well and said second well.

There is further provided in accordance with the invention, an interface device for interfacing between classic field effect transistor (FET) circuitry and quantum circuitry, comprising a substrate, a classic FET well constructed on said substrate and operative to be connected to classic FET circuitry to form a classic side, a quantum dot well constructed on said substrate and operative to interface with quantum circuitry to form a quantum side, a control gate constructed over at least a portion of said quantum dot well, wherein a first pulse signal at a first time instance applied to said control gate controls tunneling of a single quantum particle through a local depleted tunnel path from said classic side to said quantum side in an injector mode of operation, and wherein a second pulse signal at a second time instance applied to said control gate allows tunneling of a single quantum particle through a local depleted tunneling path from the said quantum side to said classic side in a detector mode of operation.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is explained in further detail in the following exemplary embodiments and with reference to the figures, where identical or similar elements may be partly indicated by the same or similar reference numerals, and the features of various exemplary embodiments being combinable. The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:

FIG. 1 is a high level block diagram illustrating an example quantum computer system constructed in accordance with the present invention;

FIG. 2 is a high level block diagram illustrating a quantum structure and its interface using integrated electronic control circuitry;

FIG. 3A is a diagram illustrating a quantum structure before initialization;

FIG. 3B is a diagram illustrating an example ideal and decoherence Rabi oscillation waveform;

FIG. 3C is a diagram illustrating a quantum structure initialized to a first base state;

FIG. 3D is a diagram illustrating an example Rabi oscillation waveform at initialization;

FIG. 3E is a diagram illustrating a quantum structure initialized to a second base state;

FIG. 3F is a diagram illustrating an example waveform having half the Rabi oscillation period;

FIG. 3G is a diagram illustrating a quantum structure with a particle in two qdots at the same time;

FIG. 3H is a diagram illustrating an example waveform having one quarter the Rabi oscillation period;

FIG. 3I is a diagram illustrating a first quantum structure with a particle split between two qdots at the same time;

FIG. 3J is a diagram illustrating an example waveform having a period less than one quarter the Rabi oscillation period;

FIG. 3K is a diagram illustrating a second quantum structure with a particle split between two qdots at the same time;

FIG. 3L is a diagram illustrating an example waveform having a period more than one quarter the Rabi oscillation period;

FIG. 4A is a diagram illustrating a circular shaped quantum structure incorporating local depleted well tunneling;

FIG. 4B is a diagram illustrating the change in the aperture tunnel barrier from a wide depletion region to a narrow depletion region;

FIG. 4C is a diagram illustrating a first rectangular shaped quantum structure incorporating local depleted well tunneling;

FIG. 4D is a diagram illustrating the change in the aperture tunnel barrier from a wide depletion region to a narrow depletion region;

FIG. 5 is a diagram illustrating a second rectangular shaped quantum structure incorporating local depleted well tunneling;

FIG. 6 is a diagram illustrating a cross section of an example quantum structure;

FIG. 7A is a diagram illustrating an example circular shape for the quantum structure of the present invention;

FIG. 7B is a diagram illustrating an example square shape for the quantum structure of the present invention;

FIG. 7C is a diagram illustrating an example square shape with rounded corners for the quantum structure of the present invention;

FIG. 7D is a diagram illustrating an example hexagonal shape for the quantum structure of the present invention;

FIG. 7E is a diagram illustrating an example rectangular shape for the quantum structure of the present invention;

FIG. 7F is a diagram illustrating an example trapezoidal shape for the quantum structure of the present invention;

FIG. 7G is a diagram illustrating a first example overlapping square shape for the quantum structure of the present invention;

FIG. 7H is a diagram illustrating a first example ‘L’ shape for the quantum structure of the present invention;

FIG. 7I is a diagram illustrating an example ‘Z’ shape for the quantum structure of the present invention;

FIG. 7J is a diagram illustrating a second example ‘L’ shape for the quantum structure of the present invention;

FIG. 7K is a diagram illustrating an example barely touching square shape for the quantum structure of the present invention;

FIG. 7L is a diagram illustrating an example barely touching square shape with optical proximity control for the quantum structure of the present invention;

FIG. 7M is a diagram illustrating an example double square with narrow neck shape for the quantum structure of the present invention;

FIG. 7N is a diagram illustrating a second example overlapping square shape for the quantum structure of the present invention;

FIG. 7O is a diagram illustrating a third example overlapping square shape for the quantum structure of the present invention;

FIG. 7P is a diagram illustrating an example barely touching rectangular shape for the quantum structure of the present invention;

FIG. 7Q is a diagram illustrating an example barely touching double overlapping square shape for the quantum structure of the present invention;

FIG. 7R is a diagram illustrating an example double square connected via single smaller square shape for the quantum structure of the present invention;

FIG. 7S is a diagram illustrating an example double square connected via double smaller square shape for the quantum structure of the present invention;

FIG. 8A is a diagram illustrating a first example control gate for the quantum structure of the present invention;

FIG. 8B is a diagram illustrating a second example control gate for the quantum structure of the present invention;

FIG. 8C is a diagram illustrating a third example control gate for the quantum structure of the present invention;

FIG. 9A is a diagram illustrating an example quantum structure with double square shape;

FIG. 9B is a diagram illustrating an example quantum structure with double square shape and optical proximity control;

FIG. 9C is a diagram illustrating an example quantum structure with double square and narrow neck shape;

FIG. 9D is a diagram illustrating a first example quantum structure with double overlapping square shape;

FIG. 9E is a diagram illustrating a second example quantum structure with double overlapping square shape;

FIG. 9F is a diagram illustrating an example quantum structure with ‘L’ shape;

FIG. 9G is a diagram illustrating an example quantum structure with double rounded barely touching square shape;

FIG. 9H is a diagram illustrating an example quantum structure with double rectangular shape;

FIG. 9I is a diagram illustrating an example quantum structure with double square connected via double smaller square shape;

FIG. 9J is a diagram illustrating an example quantum structure with double rounded square with narrow neck shape;

FIG. 9K is a diagram illustrating an example quantum structure with an overlapping pair of double rounded squares with narrow neck shape;

FIG. 9L is a diagram illustrating a first example quantum structure with a pair of barely touching double overlapping square shape;

FIG. 9M is a diagram illustrating a second example quantum structure with a pair of barely touching double overlapping square shape;

FIG. 9N is a diagram illustrating a first example quantum structure with a double square shape with narrow neck and butterfly shaped control gate;

FIG. 9O is a diagram illustrating a second example quantum structure with a double square shape with narrow neck and butterfly shaped control gate;

FIG. 9P is a diagram illustrating an example quantum structure with a pair of overlapping double square shapes with narrow neck and butterfly shaped control gates;

FIG. 9Q is a diagram illustrating an example conventional FET with drain and source doped diffusion and contacts;

FIG. 9R is a diagram illustrating an example half conventional FET and half quantum structure;

FIG. 9S is a diagram illustrating an example quantum structure with rectangular shaped wells;

FIG. 9T is a diagram illustrating an example quantum structure with dissimilar rectangular shaped wells;

FIG. 9U is a diagram illustrating an example quantum structure with offset rectangular shaped wells;

FIG. 9V is a diagram illustrating a first example quantum structure with spaced apart rectangular shaped wells;

FIG. 9W is a diagram illustrating a first example quantum structure with spaced apart rectangular shaped wells offset from each other;

FIG. 9X is a diagram illustrating a second example quantum structure with spaced apart rectangular shaped wells;

FIG. 9Y is a diagram illustrating a second example quantum structure with spaced apart rectangular shaped wells offset from each other;

FIG. 9Z is a diagram illustrating a third example quantum structure with spaced apart rectangular shaped wells offset from each other;

FIG. 9AA is a diagram illustrating a fourth example quantum structure with spaced apart rectangular shaped wells offset from each other;

FIG. 9AB is a diagram illustrating a first example quantum structure with corner abutting rectangular shaped wells;

FIG. 9AC is a diagram illustrating a second example quantum structure with corner abutting rectangular shaped wells;

FIG. 9AD is a diagram illustrating a third example quantum structure with corner abutting rectangular shaped wells;

FIG. 9AE is a diagram illustrating a fourth example quantum structure with corner abutting rectangular shaped wells;

FIG. 9AF is a diagram illustrating a fifth example quantum structure with corner abutting rectangular shaped wells;

FIG. 9AG is a diagram illustrating a sixth example quantum structure with corner abutting rectangular shaped wells;

FIG. 10A is a diagram illustrating a first example interface device of the present invention in more detail;

FIG. 10B is a diagram illustrating a second example interface device of the present invention;

FIG. 10C is a diagram illustrating a third example interface device of the present invention;

FIG. 11 is a diagram illustrating a cross section of a first example quantum structure and conventional FET;

FIG. 12 is a diagram illustrating a cross section of a second example quantum structure and conventional FET;

FIG. 13 is a diagram illustrating a cross section of a third example quantum structure and conventional FET;

FIG. 14 is a diagram illustrating an example quantum structure with interface devices;

FIG. 15A is a diagram illustrating a first example multiple qdot quantum structure with interface devices on either end thereof;

FIG. 15B is a diagram illustrating an example layout of an example quantum structure;

FIG. 16 is a diagram illustrating a cross section of the quantum structure of FIG. 15A;

FIG. 17A is a diagram illustrating the aperture tunnel barrier for a two quantum dot structure;

FIG. 17B is a diagram illustrating a first example change in the aperture tunnel barrier for the two quantum dot structure;

FIG. 17C is a diagram illustrating a second example change in the aperture tunnel barrier for the two quantum dot structure;

FIG. 18 is a diagram illustrating an example quantum structure surrounded by a spin control magnetic coil;

FIG. 19 is a diagram illustrating a second example multiple qdot quantum structure;

FIG. 20 is a diagram illustrating a third example multiple qdot quantum structure;

FIG. 21 is a diagram illustrating a fourth example multiple qdot quantum structure;

FIG. 22A is a diagram illustrating an example floating well detection circuit;

FIG. 22B is a diagram illustrating the layout for the example floating well detection circuit;

FIG. 22C is a diagram illustrating the cross section for the floating well detection circuit;

FIG. 23A is a diagram illustrating an example floating gate detection circuit;

FIG. 23B is a diagram illustrating the layout for the example floating gate detection circuit;

FIG. 23C is a diagram illustrating the cross section for the floating gate detection circuit;

FIG. 24 is an example potential diagram for the floating gate detection circuit;

FIG. 25 is a diagram illustrating an example 3D semiconductor quantum structure using fin to fin tunneling through local depletion region;

FIG. 26 is a diagram illustrating a three dimensional view of an example 3D semiconductor quantum structure with fin to fin tunneling under control of a control gate;

FIG. 27A is a diagram illustrating a cross section, side view, and top view of an example 3D two qdot quantum structure using local fin depletion tunneling;

FIG. 27B is a diagram illustrating a cross section, side views, and top view of an example 3D multiple qdot quantum structure using local fin depletion tunneling;

FIG. 28A is a diagram illustrating two example double V fin-gate-fin structures having two wells placed in close proximity allowing quantum particles to interact;

FIG. 28B is a diagram illustrating an example 3D semiconductor quantum structure using fin-to-fin tunneling through a local depleted region with a shared well between two fin paths providing bifurcation;

FIG. 28C is a diagram illustrating an example quantum structure with dummy gates and gate cuts that separate control and dummy gates;

FIG. 28D is a diagram illustrating an example hybrid planar and 3D semiconductor quantum structure using both fin-to-fin and well-to-well tunneling through local depletion region;

FIG. 29 is a diagram illustrating an example 3D semiconductor quantum structure using fin-to-gate tunneling through oxide;

FIG. 30 is a diagram illustrating a three dimensional view of an example 3D semiconductor quantum structure using fin-to-gate and gate-to-fin tunneling through oxide;

FIG. 31 is a diagram illustrating a cross section, side view, and top view of an example 3D semiconductor quantum structure using fin-to-gate tunneling through oxide;

FIG. 32 is a diagram illustrating a cross section of an example 3D semiconductor quantum structure using fin-to-gate and gate-to-fin tunneling;

FIG. 33 is a diagram illustrating a top view of an example two qdot 3D semiconductor quantum structure using fin-to-gate tunneling through oxide;

FIG. 34A is a diagram illustrating an example double V quantum interaction structure using 3D semiconductor process with fin-to-gate tunneling;

FIG. 34B is a diagram illustrating an example quantum structure with fin-to-gate tunneling with dummy gates and cuts to create dummy fins; and

FIG. 34C is a diagram illustrating an example hybrid planar and 3D semiconductor quantum structure using both fin-to-gate and well-to-gate tunneling.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be understood by those skilled in the art, however, that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.

Among those benefits and improvements that have been disclosed, other objects and advantages of this invention will become apparent from the following description taken in conjunction with the accompanying figures. Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the invention that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments of the invention which are intended to be illustrative, and not restrictive.

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings.

The figures constitute a part of this specification and include illustrative embodiments of the present invention and illustrate various objects and features thereof. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. In addition, any measurements, specifications and the like shown in the figures are intended to be illustrative, and not restrictive. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

Any reference in the specification to a method should be applied mutatis mutandis to a system capable of executing the method. Any reference in the specification to a system should be applied mutatis mutandis to a method that may be executed by the system.

Throughout the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The phrases “in one embodiment,” “in an example embodiment,” and “in some embodiments” as used herein do not necessarily refer to the same embodiment(s), though it may. Furthermore, the phrases “in another embodiment,” “in an alternative embodiment,” and “in some other embodiments” as used herein do not necessarily refer to a different embodiment, although it may. Thus, as described below, various embodiments of the invention may be readily combined, without departing from the scope or spirit of the invention.

In addition, as used herein, the term “or” is an inclusive “or” operator, and is equivalent to the term “and/or,” unless the context clearly dictates otherwise. The term “based on” is not exclusive and allows for being based on additional factors not described, unless the context clearly dictates otherwise. In addition, throughout the specification, the meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”

The following definitions apply throughout this document.

A quantum particle is defined as any atomic or subatomic particle suitable for use in achieving the controllable quantum effect. Examples include electrons, holes, ions, photons, atoms, molecules, artificial atoms. A carrier is defined as an electron or a hole in the case of semiconductor electrostatic qubit. Note that a particle may be split and present in multiple quantum dots. Thus, a reference to a particle also includes split particles.

In quantum computing, the qubit is the basic unit of quantum information, i.e. the quantum version of the classical binary bit physically realized with a two-state device. A qubit is a two state quantum mechanical system in which the states can be in a superposition. Examples include (1) the spin of the particle (e.g., electron, hole) in which the two levels can be taken as spin up and spin down; (2) the polarization of a single photon in which the two states can be taken to be the vertical polarization and the horizontal polarization; and (3) the position of the particle (e.g., electron) in a structure of two qdots, in which the two states correspond to the particle being in one qdot or the other. In a classical system, a bit is in either one state or the other. Quantum mechanics, however, allows the qubit to be in a coherent superposition of both states simultaneously, a property fundamental to quantum mechanics and quantum computing. Multiple qubits can be further entangled with each other.

A quantum dot or qdot (also referred to in literature as QD) is a nanometer-scale structure where the addition or removal of a particle changes its properties is some ways. In one embodiment, quantum dots are constructed in silicon semiconductor material having typical dimension in nanometers. The position of a particle in a qdot can attain several states. Qdots are used to form qubits and qudits where multiple qubits or qudits are used as a basis to implement quantum processors and computers.

A quantum interaction gate is defined as a basic quantum logic circuit operating on a small number of qubits or qudits. They are the building blocks of quantum circuits, just like the classical logic gates are for conventional digital circuits.

A qubit or quantum bit is defined as a two state (two level) quantum structure and is the basic unit of quantum information. A qudit is defined as a d-state (d-level) quantum structure. A qubyte is a collection of eight qubits.

The terms control gate and control terminal are intended to refer to the semiconductor structure fabricated over a continuous well with a local depleted region and which divides the well into two or more qdots. These terms are not to be confused with quantum gates or classical FET gates.

Unlike most classical logic gates, quantum logic gates are reversible. It is possible, however, although cumbersome in practice, to perform classical computing using only reversible gates. For example, the reversible Toffoli gate can implement all Boolean functions, often at the cost of having to use ancillary bits. The Toffoli gate has a direct quantum equivalent, demonstrating that quantum circuits can perform all operations performed by classical circuits.

A quantum well is defined as a low doped or undoped continuous depleted semiconductor well that functions to contain quantum particles in a qubit or qudit. The quantum well may or may not have contacts and metal on top. A quantum well holds one free carrier at a time or at most a few carriers that can exhibit single carrier behavior.

A classic well is a medium or high doped semiconductor well contacted with metal layers to other devices and usually has a large number of free carriers that behave in a collective way, sometimes denoted as a “sea of electrons.”

A quantum structure or circuit is a plurality of quantum interaction gates. A quantum computing core is a plurality of quantum structures. A quantum computer is a circuit having one or more computing cores. A quantum fabric is a collection of quantum structures, circuits, or interaction gates arranged in a grid like matrix where any desired signal path can be configured by appropriate configuration of access control gates placed in access paths between qdots and structures that make up the fabric.

In one embodiment, qdots are fabricated in low doped or undoped continuous depleted semiconductor wells. Note that the term ‘continuous’ as used herein is intended to mean a single fabricated well (even though there could be structures on top of them, such as gates, that modulate the local well's behavior) as well as a plurality of abutting contiguous wells fabricated separately or together, and in some cases might apparently look as somewhat discontinuous when ‘drawn’ using a computer aided design (CAD) layout tool.

The term classic or conventional circuitry (as opposed to quantum structures or circuits) is intended to denote conventional semiconductor circuitry used to fabricate transistors (e.g., FET, CMOS, BIT, FinFET, etc.) and integrated circuits using processes well-known in the art.

The term Rabi oscillation is intended to denote the cyclic behavior of a quantum system either with or without the presence of an oscillatory driving field. The cyclic behavior of a quantum system without the presence of an oscillatory driving field is also referred to as occupancy oscillation.

Throughout this document, a representation of the state of the quantum system in spherical coordinates includes two angles θ and φ. Considering a unitary sphere, as the Hilbert space is a unitary state, the state of the system is completely described by the vector Ψ. The vector Ψ in spherical coordinates can be described in two angles θ and φ. The angle θ is between the vector Ψ and the z-axis and the angle φ is the angle between the projection of the vector on the XY plane and the x-axis. Thus, any position on the sphere is described by these two angles θ and φ. Note that for one qubit angle θ representation is in three dimensions. For multiple qubits θ representation is in higher order dimensions.

Semiconductor Processing

Regarding semiconductor processing, numerous types of semiconductor material exist such as (1) single main atom types, e.g., Silicon (Si), Germanium (Ge), etc., and (2) compound material types, e.g., Silicon-Germanium (SiGe), Indium-Phosphide (InP), Gallium-Arsenium (GaAs), etc.

A semiconductor layer is called intrinsic or undoped if no additional dopant atoms are added to the base semiconductor crystal network. A doped semiconductor layer is doped if other atoms (i.e. dopants) are added to the base semiconductor crystal. The type of layer depends on the concentration of dopant atoms that are added: (1) very low doped semiconductor layers having high resistivity, i.e. n-type denoted by n−− and p-type denoted by p−−, having resistivities above 100 Ohm·cm; (2) low doped semiconductor layers, i.e. p-type denoted with p- and n-type denoted with n−, having resistivities around 10 Ohm·cm; (3) medium doped layers, i.e. p for p-type and n for n-type; (4) high doped layers, i.e. p+ and n+; and (5) very highly doped layers, i.e. p++ and n++.

Note that introducing dopants in a semiconductor crystal likely results in defects that introduce energy traps that capture mobile carriers. Traps are detrimental for semiconductor quantum structures because they capture and interact with the quantum particles resulting in decoherence of the quantum information. For realizing semiconductor quantum structures undoped semiconductor layers are preferred.

Classic electronic devices use mostly low, medium, high and very highly doped semiconductor layers. Some layers are ultra-highly doped to behave as metals, such as the gate layer.

Semiconductor processing is typically performed on large semiconductor wafers which have a given thickness for mechanical stability. Circuitry is fabricated on a very thin layer on the top of the wafer where the unused thick portion of the wafer is termed the substrate. In a bulk process, devices are fabricated directly in the semiconductor body of the wafer.

An insulating layer (e.g., oxide) isolates from the substrate the devices used to create circuitry. Semiconductor on insulator process, e.g., silicon on insulator (SOI), uses a layer of insulator (e.g., oxide) between the thin top semiconductor layer where devices are realized and the substrate.

To improve circuit performance, the wafer is processed such that the devices are realized on top of an insulator substrate, e.g., semiconductor-on-glass, semiconductor-on-organic material, semiconductor-on-sapphire, etc.

Alternatively, the semiconductor substrate is eliminated and replaced with a nonelectrical conducting material such as a polymer or other material compatible with a semiconductor process (e.g., substrate-replacement processes). Substrate replacement in realizing semiconductor quantum structures significantly reduces or eliminates substrate decoherence.

High resistivity (i.e. very low doped) substrates are the next best substrate choice for semiconductor quantum structures. Although intrinsic substrates are also suitable for semiconductor quantum structures, there are specific limitations that prevent the use of intrinsic substrates.

Thus, in accordance with the invention, semiconductor quantum structures can be realized in (1) bulk processes, (2) SOI processes, (3) substrate replacement processes, or (4) semiconductor on other materials.

Regarding processing, (1) planar processes may be used where layers have predominantly one orientation, i.e. horizontal; and (2) three-dimensional processes (3D) allow layers with both horizontal and vertical orientation, realizing more complex 3D structures. It is appreciated that although layers are shown in the figures as rectangular prisms for simplicity, physically the layers have more complicated structures. For example, corners are often rounded and distortions are present due to the masking process. In depth dimension, layers tend to have a trapezoidal shape instead of the ideal rectangular one. The semiconductor quantum structures of the present invention can be realized in either planar or 3D processes.

Quantum Computing System

A high-level block diagram illustrating a first example quantum computer system constructed in accordance with the present invention is shown in FIG. 1. The quantum computer, generally referenced 10, comprises a conventional (i.e. not a quantum circuit) external support unit 12, software unit 20, cryostat unit 36, quantum processing unit 38, clock generation units 33, 35, and one or more communication busses between the blocks. The external support unit 12 comprises operating system (OS) 18 coupled to communication network 76 such as LAN, WAN, PAN, etc., decision logic 16, and calibration block 14. Software unit 20 comprises control block 22 and digital signal processor (DSP) 24 blocks in communication with the OS 18, calibration engine/data block 26, and application programming interface (API) 28.

Quantum processing unit 38 comprises a plurality of quantum core circuits 60, high speed interface 58, detectors/samplers/output buffers 62, quantum error correction (QEC) 64, digital block 66, analog block 68, correlated data sampler (CDS) 70 coupled to one or more analog to digital converters (ADCs) 74 as well as one or more digital to analog converters (DACs, not shown), clock/divider/pulse generator circuit 42 coupled to the output of clock generator 35 which comprises high frequency (HF) generator 34. The quantum processing unit 38 further comprises serial peripheral interface (SPI) low speed interface 44, cryostat software block 46, microcode 48, command decoder 50, software stack 52, memory 54, and pattern generator 56. The clock generator 33 comprises low frequency (LF) generator 30 and power amplifier (PA) 32, the output of which is input to the quantum processing unit (QPU) 38. Clock generator 33 also functions to aid in controlling the spin of the quantum particles in the quantum cores 60.

The cryostat unit 36 is the mechanical system that cools the QPU down to cryogenic temperatures. Typically, it is made from metal and it can be fashioned to function as a cavity resonator 72. It is controlled by cooling unit control 40 via the external support unit 12. The cooling unit control 40 functions to set and regulate the temperature of the cryostat unit 36. By configuring the metal cavity appropriately, it is made to resonate at a desired frequency. A clock is then driven via a power amplifier which is used to drive the resonator which creates a magnetic field. This magnetic field can function as an auxiliary magnetic field to aid in controlling one or more quantum structures in the quantum core.

The external support unit/software units may comprise any suitable computing device or platform such as an FPGA/SoC board. In one embodiment, it comprises one or more general purpose CPU cores and optionally one or more special purpose cores (e.g., DSP core, floating point, etc.) that that interact with the software stack that drives the hardware, i.e. the QPU. The one or more general purpose cores execute general purpose opcodes while the special purpose cores execute functions specific to their purpose. Main memory comprises dynamic random access memory (DRAM) or extended data out (EDO) memory, or other types of memory such as ROM, static RAM, flash, and non-volatile static random access memory (NVSRAM), bubble memory, etc. The OS may comprise any suitable OS capable of running on the external support unit and software units, e.g., Windows, MacOS, Linux, QNX, NetBSD, etc. The software stack includes the API, the calibration and management of the data, and all the necessary controls to operate the external support unit itself.

The clock generated by the high frequency clock generator 35 is input to the clock divider 42 that functions to generate the signals that drive the QPU. Low frequency clock signals are also input to and used by the QPU. A slow serial/parallel interface (SPI) 44 functions to handle the control signals to configure the quantum operation in the QPU. The high speed interface 58 is used to pump data from the classic computer, i.e. the external support unit, to the QPU. The data that the QPU operates on is provided by the external support unit.

Non-volatile memory may include various removable/non-removable, volatile/nonvolatile computer storage media, such as hard disk drives that reads from or writes to non-removable, nonvolatile magnetic media, a magnetic disk drive that reads from or writes to a removable, nonvolatile magnetic disk, an optical disk drive that reads from or writes to a removable, nonvolatile optical disk such as a CD ROM or other optical media. Other removable/non-removable, volatile/nonvolatile computer storage media that can be used in the exemplary operating environment include, but are not limited to, magnetic tape cassettes, flash memory cards, digital versatile disks, digital video tape, solid state RAM, solid state ROM, and the like.

The computer may operate in a networked environment via connections to one or more remote computers. The remote computer may comprise a personal computer (PC), server, router, network PC, peer device or other common network node, or another quantum computer, and typically includes many or all of the elements described supra. Such networking environments are commonplace in offices, enterprise-wide computer networks, intranets and the Internet.

When used in a LAN networking environment, the computer is connected to the LAN via network interface 76. When used in a WAN networking environment, the computer includes a modem or other means for establishing communications over the WAN, such as the Internet. The modem, which may be internal or external, is connected to the system bus via user input interface, or other appropriate mechanism.

Computer program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++, C# or the like, conventional procedural programming languages, such as the “C” programming language, and functional programming languages such as Python, Hotlab, Prolog and Lisp, machine code, assembler or any other suitable programming languages.

Also shown in FIG. 1 is the optional data feedback loop between the quantum processing unit 38 and the external support unit 12 provided by the partial quantum data read out. The quantum state is stored in the qubits of the one or more quantum cores 60. The detectors 62 function to measure/collapse/detect some of the qubits and provide a measured signal through appropriate buffering to the output ADC block 74. The resulting digitized signal is sent to the decision logic block 16 of the external support unit 12 which functions to reinject the read out data back into the quantum state through the high speed interface 58 and quantum initialization circuits. In an alternative embodiment, the output of the ADC is fed back to the input of the QPU.

In one embodiment, quantum error correction (QEC) is performed via QEC block 64 to ensure no errors corrupt the read out data that is reinjected into the overall quantum state. Errors may occur in quantum circuits due to noise or inaccuracies similarly to classic circuits. Periodic partial reading of the quantum state function to refresh all the qubits in time such that they maintain their accuracy for relatively long time intervals and allow the complex computations required by a quantum computing machine.

It is appreciated that the architecture disclosed herein can be implemented in numerous types of quantum computing machines. Examples include semiconductor quantum computers, superconducting quantum computers, magnetic resonance quantum computers, optical quantum computers, etc. Further, the qubits used by the quantum computers can have any nature, including charge qubits, spin qubits, hybrid spin-charge qubits, etc.

In one embodiment, the quantum structure disclosed herein is operative to process a single particle at a time. In this case, the particle can be in a state of quantum superposition, i.e. distributed between two or more locations or charge qdots. In an alternative embodiment, the quantum structure processes two or more particles at the same time that have related spins. In such a structure, the entanglement between two or more particles could be realized. Complex quantum computations can be realized with such a quantum interaction gate/structure or circuit.

In alternative embodiments, the quantum structure processes (1) two or more particles at the same time having opposite spin, or (2) two or more particles having opposite spins but in different or alternate operation cycles at different times. In the latter embodiment, detection is performed for each spin type separately.

A high level block diagram illustrating a generalized quantum structure interfaced to classical integrated electronic control circuitry is shown in FIG. 2. The example quantum circuit, generally referenced 80, comprises quantum structure 84 at its core, and support circuitry that in one embodiment is integrated on the same physical realized support or external on a different physical realized support. The support circuitry comprises reset circuits 82 for flushing the quantum structure of any available free carriers before starting the quantum operation and to prepare it for a new quantum operation, injector circuits 88 that function to inject one or more particles into the quantum core structure, imposer circuits 90 that control the quantum operation and the flow of the quantum computation between the injected particles, detector circuits 86 that sense whether a particle is present or not in the output qdots and the particles at the output points of the quantum structure after the quantum operation has been performed, and control circuitry 92. Note that in one embodiment, multiple such quantum structures/quantum cores can be interconnected and/or operated in parallel. Further note that the common electrical node of the reset circuit 82 output and the injector circuit 88 output can be the same as the electrical node of the detector circuit (86) input. In this case, the three circuits time-share their active operations.

To achieve quantum operation, physical structures must be cooled to cryogenic temperatures and be isolated as much as possible from environmental perturbations (e.g., external electric fields and/or magnetic fields, etc.). To perform quantum computing using particles in a semiconductor structure, the particles (e.g., electrons, holes, etc.) need to be able to be excited in quantum states and to stay in such states for a long enough time for the operation and measurement of the quantum operation to be realized. At higher temperatures, the thermal energy of the particle results in the decoherence of its quantum state.

In one embodiment, the semiconductor based quantum structure uses a continuous well with an imposing gate that generates a controlled local depletion region to separate two or more regions of the well that form quantum dots (qdots). By modulating the potential of the imposer gate, controlled tunneling through the local depleted region is enabled between the plurality of sections of the continuous well, realizing the function of a position/charge qubit. It is appreciated that more complex structures having a higher number of qdots per continuous well and a larger number of wells can be built using the techniques of the present invention. Both planar and 3D semiconductor processes can be used to build such well-to-well tunneling quantum structures. By combining a number of such elementary quantum structures/gates, a quantum computing machine is realized.

Quantum Operation

To aid in understanding the principles of the present invention, a brief explanation of quantum operation is presented below.

As stated supra, in classic electronics, the unit of information is a bit that can represent only one of the two states “0” and “1” at a given time. Computations in classical computers are performed sequentially and every bit can hold only one state at a time.

As stated supra, quantum electronics uses the quantum behavior of particles to perform computations. The unit of quantum information is a quantum bit or qubit. A qubit has two or more base states denoted by {circumflex over (0)} and {circumflex over (1)} (or |0> and |1>) but in contrast with a classic bit, a qubit can be in a superposed state that contains some percentage ‘a’ of state 6, and some percentage ‘b’ of state {circumflex over (1)}, denoted by a{circumflex over (0)}+b{circumflex over (1)}. Since a qubit in quantum structures can simultaneously be in multiple superposed states, multiple sets of computations can be performed concurrently, resulting in large quantum computation speed-ups, when compared with classic computations.

A quantum particle is described by its position and/or spin. The particles used in quantum structures are called quantum particles. There are qubits based on the quantum position of the particles, also named charge-qubits, while other qubits use the spin of the quantum particles, also named spin-qubits. In quantum structures, the charge carriers are held in specific regions called quantum dots or qdots. A quantum structure is constructed from one or more qdots.

Performing a quantum computation involves several steps. First the structure needs to be reset, which means that all the free carriers (e.g., electrons or holes) from the structure need to be flushed out. Once the free carriers are removed, the structure is initialized meaning particles are introduced in one of the base states (e.g., {circumflex over (0)} or {circumflex over (1)}). In the case of a charge-qubit (position-qubit) it means that a carrier is loaded in one of the qdots. A free carrier not coming from the quantum initialization process can interact with the quantum particles and result in decoherence, i.e. loss of quantum information. After the particles have been loaded in the corresponding base states they undergo the desired quantum operation under control of gate control terminals. Once the desired quantum operations are complete a detection is performed whereby the presence or absence of a particle in a given qdot at a given time is tested. Detection is usually destructive which means that the quantum particle's wavefunction and its state collapse. Special nondestructive detection/measurement exist that do not collapse the quantum state. In such cases, multiple measurements of the same quantum state can be performed.

The position of a quantum particle is given by the region where the particle wave-function is mostly present. In one embodiment, quantum structures use semiconductor qdots realized with semiconductor wells where the particle transport is done through tunneling which is a quantum effect. The tunneling or particle transport is controlled by control terminals. In one embodiment, the control terminals are realized using gates but they may comprise other semiconductor process layers.

To illustrate, consider a generic position double qdot structure having a “dog bone” shape shown in FIG. 3A. The structure comprises a control gate 974 giving rise to two qdots 970, 972, that correspond to the |0> and |1> base states, or “left” and “right” base states, when an electrostatic particle happens to be there. Higher order position quantum structures can be realized having more than two base states and thus use more than two qdots. The particle transport from one qdot to the other is done through tunneling. Before initialization both qdots must be cleared of quantum particles since a reset flushes out all free carriers.

Note that a key difference between the classic and quantum structures/circuits is that the structure can not only be in the base states |0> and |1>, but also in a superposed position a|0>+b|1>, with a constraint |a|²+|b|²=1, meaning the particle is present simultaneously in both qdots of the structure. When the signal on the control terminal causes a lowering of the tunneling barrier, the particle initially loaded in the left qdot 970 will tunnel to the right qdot 972. The position of the particle and thus the corresponding quantum state is given by the pulse width of the signal V_(control) applied to the control gate. If the pulse width is long enough, after the particle has tunneled to the right qdot 972 it will tunnel back to the left qdot 970 and then again to the right qdot 972 and the process repeats itself in an oscillatory fashion. The period of this oscillation, called the Rabi oscillation (especially in case of a time-dependent Hamiltonian), depends on the tunnel current and thus on the control signal V_(control) applied and the configuration and process of the specific structure. The time needed for a particle to tunnel forward and then back to its initial position is called the Rabi period.

The Rabi oscillation after reset but before initialization is shown in FIG. 3B where waveform 976 represents an ideal oscillation and waveform 978 represents oscillation with some amount of decoherence or leakage of wavefunction.

Consider a quantum particle 976 loaded in the left qdot 970 with a base state |0>, as shown in FIG. 3C. The Rabi oscillation waveform at initialization (dot referenced 980) is shown in FIG. 3D. In a horizontally oriented double qdot, a quantum particle 976 loaded in the right qdot 972 is considered in the base state |1>, as shown in FIG. 3E. Similarly, the up and down qdots correspond to the |0> and |1> base states in a vertically oriented double qdot. The control terminal (typically the gate) determines the height of the tunnel barrier. If the potential barrier is high then tunneling is blocked (i.e. negligible). On the other hand, if the potential barrier is low then tunneling is allowed and the particle moves from one qdot to the other, resulting in a change in quantum state.

If the control signal pulse width is equal to half the Rabi period as shown in FIG. 3F, then the particle will tunnel from the left qdot 970 to the right qdot 972, i.e. transition from the |0> base state to the |1> base state also known as a quantum inversion, trajectory of which is represented by waveform solid portion 982.

If the control pulse width is equal to one quarter of the Rabi period as represented by waveform solid portion 984 trajectory in FIG. 3H, then the particle will be present equally in the left qdot 970 and in the right qdot 972 as shown in FIG. 3G. This equal distribution quantum state is called the Hadamard state and is fundamental for quantum computation. The double qdot with a quarter Rabi period control signal performs the function of a fundamental Hadamard quantum gate. Considering the sinewave of an oscillatory effect, the Hadamard state corresponds to the zero crossings, while the peak of the positive cycle corresponds to the base state |0> and the peak of the negative cycle corresponds to the base state |1>. All points between the positive and negative peaks correspond to superposition states.

If the pulse width of the control signal is less than one quarter the Rabi period as represented by solid waveform portion 986 in FIG. 3J, then the quantum particle is split between the two qdots as shown in FIG. 3I but it will have a larger presence in the left qdot 970 versus the right qdot 972. Similarly, if the pulse width is larger than one quarter the Rabi period as represented by solid waveform portion 988 in FIG. 3L, than the quantum particle is split as shown in FIG. 3K but will have a larger presence in the right qdot 972.

If the position of the particle is represented as a vector of constant length in a circular coordinate system, a vector pointing up represents the |0> base state, while a vector pointing down represents the |1> base state. Any other position is a superposed state that constitutes a quantum rotation operation. As such the double qdot quantum structure with a variable control signal pulse width constitutes a controlled quantum rotation gate.

The initialization of a quantum structure is realized by an interface device (described in more detail infra) having one side connected to classical circuitry and the other side connected to quantum circuitry, i.e. half classic, half quantum. On the classic side, the carriers (e.g., electrons or holes) have a collective behavior, sometimes called a sea of electrons (or holes). On the quantum side, the carriers exhibit single charge carrier or a few carrier behavior and their interaction is based on the laws of quantum mechanics. Injecting exactly a single particle in the quantum structure at a given qdot can be realized through the tunneling effect in the interface device. Once a single particle has tunneled, the electric field changes such that it opposes the tunneling of a subsequent particle. Such behavior of the interface device is critical to be able to inject one or multiple single particles into one or multiple qdots of a given quantum structure.

The pulse width of the control signals can be digitally controlled on the classical side of the circuits and thus determine what kind of quantum operation is performed, resulting in a programmable quantum machine. In this case, the same hardware implementation is able to perform different quantum operations based on the specific control signal applied.

Note that each quantum particle injected into the quantum structure represents a qubit. In the position qubit at least two qdots are needed to implement a qubit. In the general case, structures with N qubits and M qdots can be constructed. The number of injectors, however, should be equal to N if all particles are injected at the same time, or it can be lower than N if the particles are injected at different times.

A diagram illustrating a circular shaped semiconductor quantum structure incorporating local depleted well tunneling is shown in FIG. 4A. The quantum structure, generally referenced 100, comprises a continuous well with a local depleted region with a control gate 106 fabricated over it that functions to separate the well into two or more portions each implementing a qdot. In this example, the continuous well is split into two qdots 102, 104 with a tunneling path 108 formed between them for the quantum particle 110, e.g., electron, to tunnel through. The tunneling path 108 is considered to effectively connect the two wells 102 and 104 in a quantum manner. The quantum operation is controlled by the gate 106 fabricated over the tunneling path 108. The gate functions to modulate the energy barrier created by the local depleted region. The two sections of the well, the tunneling path with the local depleted region, and the control gate can take any number of different shapes (described infra) allowed by the particular semiconductor process used (planar or 3D).

In one embodiment, the two qdots 102, 104 are linked by a region 108 that is partially or completely locally depleted and in which tunneling occurs as indicated by arrow 109 through the tunneling path. The control gate typically overlaps the tunneling path in order to maintain well-controlled depletion of the entire linking region between the two qdots. This prevents direct electric conduction between the two qdots.

The depletion region is required for quantum operation of the structure. If there were no depletion region, the operation would revert to a classical transistor operation in on/off modes and the particle can normally move from one side to the other. Note that the probability of a particle tunneling through the depletion region is approximately exponentially linked to the width of the depletion region. If the depletion region is very narrow, the particle will tunnel and the quantum operation is achieved. If the depletion region is wide, then there is no tunneling or the tunneling is so weak that it can be neglected. This is also dependent on the tunneling barrier height. For a p-type semiconductor material, placing a positive potential on the gate will repel the holes and create a depletion region. Note that the voltage is necessarily lower than the level that results in the creation of an inversion channel.

The control signals that need to be applied to the gate depend on whether the semiconductor material is p or n type. Consider for example p-type semiconductor material, with no potential on the gate, the particle may be free to tunnel. Placing a positive potential on the gate will repel the particles (i.e. holes) and create the depletion region thereby hindering tunneling. If the potential on the gate is removed or brought closer to zero to zero or made negative, the particles are permitted to tunnel in relation to the potential applied. The operation of the quantum structure is significantly different than that of a conventional transistor.

In one embodiment, the two qdots 102, 104 are realized by a single semiconductor well having a polysilicon gate on top. The tunneling happens laterally or horizontally through the depleted region that isolates the two qdots.

Note also that in one embodiment the well is surrounded by oxide, isolating layers, and/or one or more wide depletion regions that prevent the quantum particle from escaping from the well.

A diagram illustrating the change in the aperture tunnel barrier from a wide depletion region to a narrow depletion region is shown in FIG. 4B. To contain or trap the quantum particle 114, the barrier potential 112 between the two wells is made high (dashed line 116). Lowering the barrier potential between the two wells (solid line below the dashed line) enables the quantum particle to tunnel from one qdot to the other.

A diagram illustrating a first rectangular shaped semiconductor quantum structure incorporating local depleted well tunneling is shown in FIG. 4C. The quantum structure, generally referenced 120, is similar to structure 100 of FIG. 4A apart from the dog bone shape of the continuous local depleted well. Control gate 126 is fabricated over the well and functions to separate the well into two qdots 122, 124 with tunneling path 128 formed between them for the quantum particle 130 to tunnel through. The quantum operation is controlled by the gate 126 fabricated over the tunneling path 128. The gate functions to modulate the barrier created by the local depleted region.

The two qdots 122, 124 are linked by a region 128 that is partially or completely locally depleted and in which tunneling occurs as indicated by arrow 129 through the tunneling path. The control gate typically overlaps the tunneling path in order to maintain well-controlled depletion of the entire linking region between the two Qdots. This prevents direct electric conduction between the two qdots.

A diagram illustrating the change in the aperture tunnel barrier from a wide depletion region to a narrow depletion region is shown in FIG. 4D. To contain or trap the quantum particle 134, the barrier potential 132 between the two wells is made high (dashed line 136). Lowering the barrier potential (solid line) enables the quantum particle to tunnel from one qdot to the other.

A diagram illustrating a second rectangular shaped semiconductor quantum structure incorporating local depleted well tunneling is shown in FIG. 5. The quantum structure, generally referenced 140, is similar to structure 100 of FIG. 4A apart from the ‘S’ shape of the continuous well with local depleted region. Control gate 146 is fabricated over the well and functions to separate the well into two qdots 142, 144 with tunneling path 148 formed between them for the quantum particle 149 to tunnel through. The quantum operation is controlled by the gate 146 fabricated over the tunneling path 148. The gate functions to modulate the barrier created by the local depleted region.

The two qdots 142, 144 are linked by a region 148 that is partially or completely locally depleted and in which tunneling occurs as indicated by arrow 147 through the tunneling path. The control gate typically overlaps the tunneling path in order to maintain well-controlled depletion of the entire linking region between the two Qdots. This prevents direct electric conduction between the two qdots.

A diagram illustrating a cross section of an example semiconductor quantum structure 150 is shown in FIG. 6. An exemplary cross section in a silicon-on-insulator (SOI) process is shown in which the substrate 152 is low doped (i.e. high resistivity) and is isolated from the quantum device with a buried oxide layer (BOX) 154. This reduces the decoherence of the quantum particle. In one embodiment, the semiconductor quantum device employs tunneling through the local depleted region. In another embodiment, tunneling occurs through the oxide layer between the semiconductor well 160 (low doped or undoped) and the partially overlapping gate 158 and oxide layer 166. The active layer 160 is isolated using oxide from adjacent structures, e.g., shallow trench isolation (STI) 156, reducing further the quantum particle decoherence.

Note that the substrate may comprise (1) a semiconductor, (2) silicon on insulator (SOI) substrate, where the substrate comprises sapphire, glass, organic material, etc., (3) an insulating substrate replacement, for example, sapphire, glass, organic material, plastic, polymer, etc., or (4) any other insulating material compatible with a semiconductor process.

Note that regardless of the substrate used, the quantum structure must be electrically isolated from the substrate for the structure to operate properly. Otherwise, the quantum particle may escape thus preventing quantum operation of the structure.

Several ways to electrically isolate the quantum structure include: (1) utilizing an SOI or low doped substrate where the oxide layer electrically isolates the quantum structure from the substrate; (2) using substrate replacement such as an insulator material, e.g., polymer, glass, etc.; and (3) using a fixed depletion region, as the quantum particle can tunnel only through a relatively narrow insulating region such as very thin oxide or a thin depletion region. If the depletion region is too wide, the quantum particle is prevented from traveling. Note that this last option can be fabricated using bulk processes.

The quantum operation is controlled by the gate located over the tunneling path that modulates the barrier created by the local depletion region.

In one embodiment, a low doped substrate interacts with the quantum particle with far and weak interactions. Tunneling of the quantum particle 162 occurs in region 164 between the two qdots formed in the active layer 160 and the tunnel path may be straight through from one qdot to the other (see dashed arrow 168) or may take a path through the gate and back to the active layer (see dashed arrow 169). Alternatively, the substrate may comprise a substrate replacement that includes non-conducting material, e.g., polymer, glass, sapphire, without free charge or ions that can interact with the quantum particle.

In both cases, the active well is preferably isolated on all sides (i.e. typically with oxide) where the particles are permitted to travel only through a narrow link where tunneling occurs.

Alternatively, bulk semiconductor processes are used where the substrate 152 is isolated from the quantum device using a large depleted region under the quantum gate instead of BOX. In another alternative embodiment, the quantum device is placed directly into the substrate. The quantum device can be isolated laterally from other devices using oxide layers 156 (e.g., STI or another preferably low doped well). In another alternative embodiment, a bulk semiconductor quantum structure replaces the substrate with an isolator material 152 having no free carriers or ions that can interact with the quantum particle. In an alternative embodiment, a substrate replacement process or a semiconductor on insulator process can also be used.

The cross section 150 shows the quantum structure with well-to-well tunneling through the local depleted region. It is noted that if the depleted region 164 is wide, then no or negligible tunneling 168 is present. If under the control of the gate the tunneling barrier is lowered and the depletion region gets narrower, a sizeable tunneling current may occur, resulting in the quantum particle tunneling from one qdot to the other.

Note that tunneling is also possible from the well to the gate and then from the gate to the adjacent well, bypassing the local depleted area (arrow 169). The width of the depleted area, however, can be made narrower than the thin gate oxide and thus the predominant tunneling can be made to be through the local depleted region.

In some cases, the gate oxide thickness is reduced using special materials such as hafnium oxide. The tunneling barrier height, however, is still high and tunneling is likely to happen through the depletion layer.

In accordance with the present invention, the quantum structure may comprise numerous shapes and sizes constrained only by design rule check (DRC) of the particular semiconductor process used to fabricate the structure. Several examples of quantum structure shapes, e.g., circles, squares, rectangles, polygons, etc. will now be described. In each case, these shapes can be used for the constituent layers and for one or more qdots making up the quantum structure.

A double qdot quantum structure which is the elementary structure for position qubit quantum computing contains two quantum dots and a tunneling path (often narrow) between them.

Quantum Structure Shapes

A diagram illustrating an example circular shape 170 for the quantum structure of the present invention is shown in FIG. 7A. A diagram illustrating an example square shape 172 for the quantum structure of the present invention is shown in FIG. 7B. A diagram illustrating an example square shape with rounded corners 174 for the quantum structure of the present invention is shown in FIG. 7C. A diagram illustrating an example hexagonal shape 176 for the quantum structure of the present invention is shown in FIG. 7D. A diagram illustrating an example rectangular shape 178 for the quantum structure of the present invention is shown in FIG. 7E.

A diagram illustrating an example trapezoidal shape 180 for the quantum structure of the present invention is shown in FIG. 7F. A diagram illustrating a first example overlapping square shape 182 for the quantum structure of the present invention is shown in FIG. 7G. A diagram illustrating a first example ‘L’ shape 184 for the quantum structure of the present invention is shown in FIG. 7H. A diagram illustrating an example ‘S’ shape 186 for the quantum structure of the present invention is shown in FIG. 7I. A diagram illustrating a second example ‘L’ shape 188 for the quantum structure of the present invention is shown in FIG. 7J.

A diagram illustrating an example barely touching squares shape 189 for the quantum structure of the present invention is shown in FIG. 7K. Note that in this example shape and others it is preferable that the squares overlap as little as possible since it is desirable to have as narrow a tunneling region as possible to maximize control. A large tunneling area is more difficult to control and to deplete sufficiently to prevent partial or complete tunneling.

A diagram illustrating an example barely touching square shape 190 with optical proximity control 192 for the quantum structure of the present invention is shown in FIG. 7L. A diagram illustrating an example double squares 194 with narrow neck 196 shape for the quantum structure of the present invention is shown in FIG. 7M. A diagram illustrating a second example overlapping square shape 198 for the quantum structure of the present invention is shown in FIG. 7N. A diagram illustrating a third example overlapping square shape 200 for the quantum structure of the present invention is shown in FIG. 7O.

A diagram illustrating an example barely touching rectangular shape 202 for the quantum structure of the present invention is shown in FIG. 7P. A diagram illustrating an example barely touching double overlapping squares shape 222 for the quantum structure of the present invention is shown in FIG. 7Q. A diagram illustrating an example double squares connected via single smaller square shape 208 for the quantum structure of the present invention is shown in FIG. 7R. A diagram illustrating an example double squares connected via double smaller squares shape 204 for the quantum structure of the present invention is shown in FIG. 7S.

Several alternative ways of imposing the potential on the control gate will now be described. For illustration purposes only, double overlapping square shapes are used for the qdots. It is appreciated that other shapes may be used with each technique without departing from the scope of the invention. Note that the width of the tunneling section of the continuous well in each case is preferably as small as possible, but can vary in size based on the given DRC of the semiconductor process used.

Control Gate

A diagram illustrating a first example control gate for the quantum structure of the present invention is shown in FIG. 8A. The quantum structure, generally referenced 220, comprises a floating control gate 226 with an adjacent gate 222 that is in close proximity thereto that imposes potential to the gate 226 of the double overlapping square shaped qdots 224 with tunnel path 228. Note that changing the potential of the overlapping control gate is operative to modulate the tunnel barrier height.

A diagram illustrating a second example control gate for the quantum structure of the present invention is shown in FIG. 8B. The quantum structure, generally referenced 230, comprises a metal control gate 232 imposing on the floating control gate 234 using adjacent or overlap positioning over the control gate 234 of the double overlapping square shaped qdots 236 with tunnel path 238.

A diagram illustrating a third example control gate for the quantum structure of the present invention is shown in FIG. 8C. The quantum structure, generally referenced 240, comprises a contact 244 from a metal feed 242 to a control gate 246 over double overlapping square shaped qdots 248 with tunnel path 249. The control gate is driven directly with an electrical signal (e.g., pulsed electric signal).

Quantum Structures With Control Gates

As described supra, the quantum structure may comprise numerous shapes and sizes constrained only by design rule check (DRC) of the particular semiconductor process used to fabricate the structure. Several examples of quantum structures having one or more control gates will now be described. It is important to note that there is a difference between the shapes drawn in the figures and the physical realized shapes. Further, several factors such as the semiconductor process used contribute to determining the physical shapes realized. Note also that in most cases, the link channel is mandatory for the quantum structures employing tunneling through the depletion region. The link channel, however, may not be present on the layers drawn in the figures.

Each semiconductor quantum structure disclosed uses well-to-well tunneling through a local depleted region. In order to exercise good control over the tunneling effect, the tunneling path section of the well is preferably relatively narrow when compared with the dimensions of the rest of the well that constitutes the qdots. A gate is placed on top of the tunneling path section of the well in which the local depleted region is induced. A complete overlap of the control gate on the tunneling path is preferable in order to have good control over the entire width of the tunneling path and achieve reliable isolation between the two or more sections of the continuous well that implements the quantum dots. The potential on the control gate functions to modulate the width of the local depletion region and to control the tunneling between the two adjacent sections of the well that represent two separate qdots (i.e. well-to-well tunneling). As described supra, this potential is imposed, for example, by another metal layer with no contact to gate 226 (i.e. a floating gate) as shown in FIG. 8A or with a metal layer contacted to the gate (i.e. directly driven gate) as shown in FIG. 8C. The overlapping gate is positioned such that a smaller overlap with the two adjacent sections of the well is realized resulting in a larger Coulomb blockade voltage.

A diagram illustrating an example quantum structure with double square corner touching shape is shown in FIG. 9A. The quantum structure, generally referenced 250, comprises a continuous well with control gate 254 placed over edge portions 251, 253 of the square shapes to form two qdot regions 252.

A diagram illustrating an example quantum structure with double square shape and optical proximity control is shown in FIG. 9B. The quantum structure, generally referenced 260, comprises a continuous well with control gate 264 placed over edge portions of the square shapes to form two qdot regions 262. Optical proximity control 266 is used to improve the tunnel path. As is known in the semiconductor processing arts, optical proximity correction can be used within the vicinity of the local depleted tunneling well to aid in improving the resulting structures fabricated on the substrate. Note that optical proximity correction techniques may be used with any of the structures disclosed in this document to improve the resulting structures. Note that the squares 266 shown only exist on one or more masks used in the fabrication of the structure and do not reflect any structures actually built on the substrate. These squares, however, typically have an effect on the shape of such structures constructed nearby. The desired effects include width and length adjustments of the tunneling path.

Note that in general, nanometer semiconductor processes natively yield distortions around corners and the narrow features. Optical correction helps realize physical shapes close to the desired shapes.

A diagram illustrating an example quantum structure with double square and narrow neck shape is shown in FIG. 9C. The quantum structure, generally referenced 270, comprises a continuous well with control gate 274 placed over narrow tunnel path 276 and edge portions of the square shapes to form two qdot regions 272.

A diagram illustrating a first example quantum structure with double overlapping square shape is shown in FIG. 9D. The quantum structure, generally referenced 280, comprises a continuous well with control gate 284 placed over narrow tunnel path 286 (but wider than tunnel path 296 in FIG. 9E) and edge portions of the square shapes to form two qdot regions 282.

A diagram illustrating a second example quantum structure with double overlapping square shape is shown in FIG. 9E. The quantum structure, generally referenced 290, comprises a continuous well with control gate 294 placed over narrow tunnel path 296 and edge portions of the square shapes to form two qdot regions 292.

A diagram illustrating an example quantum structure with ‘L’ shape is shown in FIG. 9F. The quantum structure, generally referenced 300, comprises a continuous well with control gate 304 placed over the transition portion of the rectangular shapes to form two qdot regions 302.

A diagram illustrating an example quantum structure with double rounded barely touching square shape is shown in FIG. 9G. The quantum structure, generally referenced 310, comprises a continuous well with control gate 314 placed over narrow tunnel path 316 and edge portions of the rounded square shapes to form two qdot regions 312.

A diagram illustrating an example quantum structure with double rectangular shape is shown in FIG. 9H. The quantum structure, generally referenced 320, comprises a continuous well with control gate 324 placed over narrow tunnel path 326 and edge portions of the rectangular shapes to form two qdot regions 322.

A diagram illustrating an example quantum structure with double square connected via double smaller square shape is shown in FIG. 9I. Optical proximity correction is used here to turn the small feature connecting shapes into a narrow continuous link channel. The quantum structure, generally referenced 330, comprises a continuous well with control gate 334 placed over double small square tunnel path 336 and edge portions of the square shapes to form two qdot regions 332.

A diagram illustrating an example quantum structure with double rounded square with narrow neck shape is shown in FIG. 9J. The quantum structure, generally referenced 340, comprises a continuous well with control gate 344 placed over contoured narrow tunnel path 346 and edge portions of the rounded square shapes to form two qdot regions 342.

A diagram illustrating an example quantum structure with an overlapping pair of double rounded squares with narrow neck shape is shown in FIG. 9K. The quantum structure, generally referenced 350, comprises a continuous well with two control gates 354 placed over a contoured narrow tunnel path 356 and edge portions of the rounded square shapes to form three qdot regions 352. Note that the middle qdot is longer, being comprised of two semiconductor squares.

A diagram illustrating a first example quantum structure with a pair of barely touching double overlapping square shape is shown in FIG. 9L. The quantum structure, generally referenced 360, comprises a continuous well with control gate 364 placed over tunnel path 366 and edge portions of the double square shapes to form two qdot regions 362.

A diagram illustrating a second example quantum structure with a pair of double corner overlapping square shape is shown in FIG. 9M. The quantum structure, generally referenced 370, comprises a continuous well with two floating control gates 374 with adjacent imposing gate potential placed over tunnel paths 378 and edge portions of the square shapes to form three qdot regions 372. Note that the middle qdot is formed by two squares of active silicon.

A diagram illustrating a first example quantum structure with a double square shape with narrow neck and butterfly shaped control gate is shown in FIG. 9N. Note that most of the quantum structures described supra comprise square or rectangular shaped gates. Some available semiconductor processes, however, allow for composed shapes for the gate. In these cases, both the well and the gate have a narrow connecting channel. The quantum structure, generally referenced 380, comprises a continuous well with control gate 382 placed over narrow tunnel path 386 to form two qdot regions 384. Here, the gate and the well both have narrow connecting channels. This structure results in a much smaller gate to well overlap resulting in a much higher Coulomb blockade voltage for the structure. This enables a higher performance of the quantum structure since a larger signal to noise ratio is achieved.

A diagram illustrating a second example quantum structure with a double square shape with narrow neck and butterfly shaped control gate is shown in FIG. 9O. Similar to the structure of FIG. 9N, the quantum structure, generally referenced 390, comprises a continuous well with control gate 392 placed over contoured narrow necked tunnel path 396 to form two rounded square qdot regions 392. Here too, the gate and the well both have narrow connecting channels.

A diagram illustrating an example quantum structure with a pair of overlapping double square shapes with narrow neck and butterfly shaped control gates is shown in FIG. 9P. The quantum structure, generally referenced 400, comprises a continuous well with two floating control gates 402 electrostatically coupled to adjacent imposing gates 406 placed over contoured narrow necked tunnel paths 408 to form three rounded square qdot regions 404 with the gates 406 and the wells having narrow connecting channels.

A diagram illustrating an example conventional field effect transistor (FET) with drain and source doped diffusion and contacts is shown in FIG. 9Q. Using a conventional field effect transistor (FET) structure to build semiconductor quantum structures results in significantly degraded performance. In one embodiment, a modified semiconductor process is used to construct optimized semiconductor quantum structures.

Conventional wells have rectangular shapes disposed parallel to each other. In one embodiment, the quantum structure uses (1) staircase well shapes that provide pairs of locations where the interaction between quantum particles/states is very strong and (2) other pairs of locations that have weak or negligible interaction between the particles situated at those locations.

The conventional FET structure, generally referenced 410, comprises drain and source doped diffusion with contacts 412 with metal on top, and gate 416 with contacts 414. This structure results in significantly higher parasitic gate capacitance since it includes the gate-to-metal, gate-to-contact and gate-to diffusion additional components. Note that in classic FET structures, carriers move either through drift under an external electric field or through diffusion due to a gradient of concentration. An inversion channel is created by a relatively large gate voltage.

A diagram illustrating an example half conventional FET and half (potentially) quantum structure is shown in FIG. 9R. In accordance with the present invention, a modified semiconductor process enables an active layer without any diffusion, contact and metal on top. The structure, generally referenced 420, comprises a conventional doped side 422 with diffusion contacts, an undoped or lightly doped quantum side 426, and gate 427 with contacts 424. Such a structure has a half-classic, half-quantum structure with one side of the gate without any n or p doping and without contacts. This type of device can be used, for example, at the interface between classic circuits and quantum circuits. In this case, the carriers move through tunneling from the classic side to the quantum side.

A diagram illustrating an example quantum structure with rectangular shaped wells is shown in FIG. 9S. The full quantum structure, generally referenced 430, does not have any n or p doping or contacts on either side. Both sides 432 of the gate 436 with contacts 434 have the same active layer width which is approximately equal to the gate width. This results in a larger gate capacitance. To reduce the parasitic gate capacitance, the width of the active layer may be made smaller than the gate width on one or both sides.

A diagram illustrating an example quantum structure with dissimilar rectangular shaped wells is shown in FIG. 9T. The structure, generally referenced 440, comprises an asymmetric aperture tunneling well with gate 446 and gate contacts 448 placed thereover to generate two qdots 442, 444 with reduced parasitic capacitance on the right side qdot.

A diagram illustrating an example quantum structure with offset rectangular shaped wells is shown in FIG. 9U. The structure, generally referenced 450, comprises an asymmetric aperture tunneling well with gate 456 and gate contacts 458 placed thereover to generate two qdots 452, 454 with both qdots having reduced parasitic capacitance.

Using active wells having different widths on the both sides of the gate reduces the parasitic gate capacitance. A more significant reduction in gate capacitance can be achieved, however, by having an active well structure having a narrow region under the gate and wider regions on either side of the gate.

A diagram illustrating a first example quantum structure with spaced apart rectangular shaped wells is shown in FIG. 9V. The structure, generally referenced 460, comprises a symmetric dog bone aperture tunneling well with gate 466 having gate contacts 468 placed thereover to generate two qdots 462, 464 with reduced parasitic capacitance on both sides. Note, however, that there remains a residual overlap of the gate and the wider active wells on the two sides of the gate. Note that the aperture refers to the narrowed link channel between the two wider well regions.

A diagram illustrating a first example quantum structure with spaced apart rectangular shaped wells offset from each other is shown in FIG. 9W. The structure, generally referenced 470, comprises an asymmetric dog bone aperture tunneling well with gate 476 and gate contacts 478 placed thereover to generate two qdots 472, 474 with reduced parasitic capacitance on both sides. Note, however, that there remains a residual overlap of the gate and the wider active wells on the two sides of the gate.

In one embodiment, to further reduce gate capacitance the overlap between the gate and the wider wells on the sides are eliminated. A diagram illustrating a second example quantum structure with spaced apart rectangular shaped wells is shown in FIG. 9X. The structure, generally referenced 480, comprises a symmetric dog bone aperture tunneling well with gate 486 and gate contacts 488 placed thereover to generate two qdots 482, 484 with reduced parasitic capacitance on both sides and no well-gate overlap in the wider regions.

A diagram illustrating a second example quantum structure with spaced apart rectangular shaped wells offset from each other is shown in FIG. 9Y. The structure, generally referenced 490, comprises an asymmetric dog bone aperture tunneling well with gate 496 and gate contacts 498 placed thereover to generate two qdots 492, 494 with reduced parasitic capacitance on both sides and no well-gate overlap in the wider regions.

As described supra, the quantum structure may be symmetric or asymmetric. The “dog-bone” quantum structure has some overhang of the wider wells passed the edge of the narrow link. The asymmetric dog bone quantum structure does not have any overhang on the narrow link side. A diagram illustrating a third example quantum structure with spaced apart rectangular shaped wells offset from each other is shown in FIG. 9Z. The structure, generally referenced 500, comprises an asymmetric dog bone aperture tunneling well with partial overlap of the gate on the wide wells and overhang passed the narrow link edges, and with gate 506 and gate contacts 508 placed thereover to generate two qdots 502, 504.

A diagram illustrating a fourth example quantum structure with spaced apart rectangular shaped wells offset from each other is shown in FIG. 9AA. The structure, generally referenced 510, comprises an asymmetric dog bone aperture tunneling well with partial overlap of the gate on the wide wells and overhang passed the narrow link edges, and with gate 516 and gate contacts 518 placed thereover to generate two qdots 512, 514 with increased gate to well capacitance, but which may ease the fabrication process.

Narrow links between the two wider wells may be realized without having them drawn as such. In one embodiment, two wells have a punctual drawn contact but during fabrication a narrow link channel is formed between the two wells using optical proximity correction. A diagram illustrating a first example quantum structure with corner abutting rectangular shaped wells is shown in FIG. 9AB. The structure, generally referenced 520, comprises an aperture tunneling well with punctual drawn link between the two wells, and with gate 526 and contacts 528 placed thereover to generate two qdots 522, 524.

A diagram illustrating a second example quantum structure with corner abutting rectangular shaped wells is shown in FIG. 9AC. The structure, generally referenced 530, comprises the physical realization of the structure of FIG. 9AB with a narrow link channel formed between the two wells using a suitable technique such as optical proximity correction channel, and with gate 536 and contacts 538 placed thereover to generate two qdots 532, 534.

Note that it is not mandatory that the two wide wells have a punctual contact in order to obtain a narrow link channel between them. In some cases, it is sufficient that they are placed in very close proximity, and optical proximity correction results in a link channel in the physically realized shapes.

A diagram illustrating a third example quantum structure with corner abutting rectangular shaped wells is shown in FIG. 9AD. The structure, generally referenced 540, comprises an aperture tunneling well without contact between the two wells but in very close proximity, and with gate 546 and contacts 548 placed thereover to generate two qdots 542, 544.

A diagram illustrating a fourth example quantum structure with corner abutting rectangular shaped wells is shown in FIG. 9AE. The structure, generally referenced 550, comprises the physical realization of the structure of FIG. 9AD with a narrow link channel formed between the two wells using a suitable technique such as optical proximity correction channel, and with gate 556 and contacts 558 placed thereover to generate two qdots 552, 554.

Note that the narrow channel link of the induced depletion region separating the two wider quantum wells can have any given orientation, e.g., horizontal, vertical, or any arbitrary angle. In addition, the control gate may overlap the narrow channel link, or it may also overlap the edges of the adjacent wider quantum wells. The former is preferred since it results in a smaller parasitic capacitance and thus a larger Coulomb blockade voltage.

A diagram illustrating a fifth example quantum structure with corner abutting rectangular shaped wells is shown in FIG. 9AF. The structure, generally referenced 560, comprises an aperture tunneling well with an angled drawn link between the two wells and gate overlap only on the link channel 569, and with gate 566 and gate contacts 568 placed thereover to generate two qdots 562, 564.

A diagram illustrating a sixth example quantum structure with corner abutting rectangular shaped wells is shown in FIG. 9AG. The structure, generally referenced 570, comprises an aperture tunneling well with an angled drawn link between the two wells and gate overlap on both the link channel 579 and the wells themselves, and with gate 576 and contacts 578 placed thereover to generate two qdots 572, 574.

It is appreciated that the fabrication of the quantum structure examples described supra is not limited to one process only but can be fabricated using any number of semiconductor processes. Examples include (1) planar semiconductor processes with depletion tunneling, (2) planar semiconductor processes with oxide tunneling, (3) 3D (FinFET) semiconductor processes with depletion tunneling, and (4) 3D (FinFET) semiconductor processes with oxide tunneling.

Single Particle Operation

It is important to note that to achieve quantum operation: (1) carriers (electrons or holes) need to be isolated, (2) information needs to be conveyed to the electrons in either their position or spin (or both), and (3) multiple carriers are allowed to interact (i.e. entangle) before a reading (referred to as detection) of the quantum state is performed.

First, single carriers are separated out of the collectivities of carriers that usually exist in semiconductor layers in classic circuits. A semiconductor layer is formed of a network of semiconductor atoms that contribute carriers to a collective of carriers described by an energy band. Dopants are introduced into semiconductor layers in order to enhance the concentration of a given type of carriers. Donor dopants increase the number of electrons yielding an N-type semiconductor layer while acceptor dopants increase the number of holes yielding a P-type semiconductor layer.

When the semiconductor contains a very large number of carriers acting as a collectivity, adding one carrier to the collectivity or subtracting one carrier from the collectivity does not change the potential. To achieve a single carrier (e.g., single electron) behavior it is best that the considered particle does not have a large collectivity of carriers that it can interact with.

An undoped semiconductor or undoped semiconductor layer has a very low concentration of carriers. It still contains a large number of carriers compared with the single carrier that is needed for quantum operations. Doped semiconductor layers have even more carriers and thus are less attractive for single electron operation.

To achieve single carrier behavior in semiconductor layers it is preferable to first deplete them of carriers before performing the single electron operations. It is relatively easy to deplete an intrinsic (i.e. undoped) semiconductor and even a low doped semiconductor. Depleting a higher doped semiconductor layer is harder and requires much larger potentials to achieve depletion. Furthermore, it is easier to deplete a thin layer of semiconductor than it is to deplete a thick layer of semiconductor. Thus, for building semiconductor quantum structures based on single electron behavior, an SOI process having a thin top active layer and an oxide layer to isolate the top layer from the substrate is preferred.

In such processes, the body of the devices is relatively easy to fully deplete. In most cases even the work function between the gate and the thin active layer is enough to generate a full depletion of the thin layer. In other cases a certain gate voltage may be needed to fully deplete the body of the device. In fully depleted processes, the thin semiconductor layer is depleted of free carriers due to the presence of one or more control gates on top.

Once the semiconductor layer is fully depleted, there are no other free carriers that can interact with the quantum particle(s) and quantum effects can come forth. In a fully depleted well (which may have initially been undoped or low doped), the potential on the control gates on top determines the its profile. Such potential profile may, for example, have valleys and peaks. The valleys is where a carrier may be likely located and the peaks constitute tunneling barriers that may prevent the particle(s) from moving from one position to another.

In such a fully depleted semiconductor layer (CAD drawn layer may be undoped or low doped) a single carrier (e.g., electron) may be injected using an interface device. The particle may be trapped in a given location in the depleted well where the potential has a valley bounded on both ends by tunnel barriers. By appropriately changing the control signals on the gate, the potential in the well and the heights of the barriers can be modified and thus the single particle may move from one location to another in the fully depleted well. This is the basis of the operation of the charge/position quantum qubit.

Classic FET transistors, on the other hand, have higher doped regions for the source and drain. In bulk processes, the higher doped source and drain regions are formed directly in the body well by implanting or diffusing dopants. In fully depleted SOI processes where a thin semiconductor film is deposited on top of the BOX oxide that provides isolation from the substrate, the source and drain regions are realized by depositing another layer of high doped semiconductor on top of the undoped thin layer.

The interface devices have on one side of the gate a higher doped layer that behaves classically and carriers that behave collectively, while under the gate and on the opposite side thereof is the original undoped layer which is fully depleted. The gate terminal determines the height of the tunnel barrier and may allow a single particle to be injected in the fully depleted well. The particle will be localized in the fully depleted well in a region where a valley of the potential is present. From this point on a quantum operation may be performed on the single carrier that was separated from the classic collectivity of carriers present on the classic well of the device.

Half Classic/Half Quantum Interface Device and Example Structures

The interface device disclosed herein is operative to provide a link between classic electronic circuits and quantum circuits. A well is a fairly isolated semiconductor layer that can be part of a device. A classic well is contacted with metal layers to other devices and usually has a large number of free carriers that behave in a collective way, sometimes denoted as a “sea of electrons.” A quantum well, however, is not connected to classic devices that may have a sea of electrons. The quantum well may or may not have contacts and metal on top, but such metal is left floating. A quantum well holds one free carrier at a time or at most a few carriers that have single carrier behavior.

The ability to inject one single carrier at a time is needed to operate a quantum structure. The charge of a carrier (i.e. electron or hole) is 1.6×10⁻¹⁹ Coulomb. The charge is the integral of the current over a given time interval. Classic devices operate with current that are usually in the 0.1 uA and higher level. If a 0.1 uA current is used to inject a single electron, the pulse width of the current needs to be 1.6'10⁻¹² sec. A pulse in the 1 ps range could require clock frequencies in the THz range if implemented straightforwardly with clocks, which are not available in current integrated semiconductor processes. Furthermore, the dependence of the transistor current on the applied voltage is relatively moderate, e.g., quadratic or even linear. Thus, in order to stop the current flow a large voltage difference is required. Such a voltage is much larger than what a typical Coulomb blockade voltage is in currently available semiconductor processes.

To stop the flow of current with a Coulomb blockade voltage, the current dependence on the voltage needs to be very steep, e.g., exponential. Such current to voltage dependencies are achieved in deep subthreshold regimes when a tunneling current is present in the device.

To inject a single electron with a pulse in the 100 ps range requires a current of 1 nA. Such a current puts the small nanometer devices in deep subthreshold mode of operation. In this regime a tunnel current with exponential voltage dependence is established between the two wells/sides of the device.

In classic electronic circuits operating at room temperature if the interface device generates a 1 nA current multiple carriers (i.e. electrons) will be transferred to the second well provided that a closed path is established for the device current. If the second well is connected electrically, there is no force that will oppose the flow of additional carriers in the second well. When the second well is left floating, a different behavior is ensured.

To achieve quantum operation the devices are cooled down to deep cryogenic temperatures such that the thermal noise or thermal agitation of the carriers is minimal. Also, the quantum devices need to use dimensions in the nanometer range, such that the capacitance of the structure is in the 100 aF range. In such cases the Coulomb blockade voltage becomes multi-millivolt level. This is needed since the transport of a single carrier from the classic well to the quantum well requires a change of potential (Coulomb blockade) large enough that the tunnel current is reduced significantly and no further carrier will tunnel to the quantum well. The dependence of the tunnel current on the potential difference between the gate and the well is exponential. Therefore, voltage changes of a few to tens of millivolts can readily stop the further tunneling of subsequent particles.

In a half-classic, half-quantum interface device the Coulomb blockade generated by the tunneling of a single carrier to the quantum well prevents other carriers from tunneling. In order to establish the initial tunneling current from the classic well to the quantum well, a potential difference is established between the well and the control gate. In one embodiment, the interface device is realized by placing a control gate over a continuous well. The potential of the gate which is directly driven or has its potential imposed for example by a capacitor divider such that a depletion region is established under the control gate thereby separating the well into two sections: one classic and one quantum. The classic well is connected to other classic devices using metal layers. In order to control the device with the gate signal, the potential of the classic well needs to be set at a certain reference value. This is done with a classic FET transistor that resets the potential of the classic well during a rest time period.

With the classic well sitting at a V_(classic_ref) potential, the potential of the gate is changed by a control signal such that a subthreshold tunnel current is generated in the interface device. The sign of the gate potential depends on the doping type, the level of the well, and the material of the gate and oxide which in turn set the work function difference. In the case of a P-type well the gate voltage needs to be more positive than the classic well potential, assuming a zero work function difference.

In this manner a pulse signal applied at the gate of the interface device determines the tunneling of precisely one particle (e.g., electron) from the classic to the quantum well. The pulse duration does not need to be very precise. It just needs to be longer than what is needed to securely tunnel a single particle. No further particle will be tunneled, even though the pulse may be longer because of the Coulomb blockade voltage that will exponentially reduce the tunnel current level.

Once a single carrier (e.g., electron or hole) is injected into the quantum well, a pure quantum operation can be performed. Using additional control gates on top of the continuous well which further isolates quantum dots in the structure, the carrier may be transported in a discrete fashion from one qdot to another. If appropriate control signal pulse widths are applied, the particle (actually, its wavefunction) may be split between two or more qdots. In one embodiment, a quantum structure can have a plurality of wells with a plurality of qdots. If the wells are brought in close proximity at least in a certain location, interaction (i.e. entanglement) between quantum particles can occur.

In one embodiment, a quantum structure comprises one or more half-classic, half-quantum interface devices. Each interface device injects a single carrier or multiple carriers but at different time instants, with one carrier at a given time.

The gate-to-classic well potential difference needed to realize the tunneling of the single carrier varies with process and location of the device. It also varies with the temperature of the structure. To mitigate such variability, the gate control signal has adjustability built-in such as via a digital to analog converter (DAC) and a calibration engine to set the appropriate voltage level for each individual injection device (i.e. half-classic, half-quantum interface device).

A diagram illustrating a first example interface device of the present invention in more detail is shown in FIG. 10A. The device, generally referenced 802, comprises a conventionally doped diffusion region 812 and one or more metal contacts 814, gate 806 and gate contacts 804, and a non-doped (intrinsic or no diffusion) or very low doped (n−−, p−−) region 820 having no or low n- or p-doping, diffusion, and no contacts nor metal. The doped diffusion region 812 is either low doped (n−, p−), medium doped (n, p), high doped (n+, p+), or highly doped (n++, p++). The doped semiconductor side 812 of the gate 806 connects to classical semiconductor electronic circuity 816, which can comprise a particle (e.g., electron) injector controller, a gate imposer controller, and a particle detector in addition to various other control, detection and processing functionalities (see FIG. 2). The gate 806 can also connect to the circuitry 816 (not shown). The non-doped side 820 of the gate 806 connects to quantum semiconductor circuits 818. Thus, half the device contains classic carriers in energy bands and the other half contains quantum carriers in discrete energy levels. The transport of carriers from the classic side to the quantum side of the device is realized through tunneling through highlighted region 808. An appropriate potential applied to the gate is operative to connect a particle from the quantum side to the classic side of the interface device. This way, the quantum particle can electrically join the potential sea of carriers. Note that the labels ‘quantum side’ and ‘classic side’ are for convenience sake since at the fundamental level there is nothing inherently quantum or classic with the two sides of the gate.

In operation, the interface device 802 functions to provide an interface from conventional electronic circuitry located on (or off) the integrated circuit to quantum circuits and vice versa. In particular, the interface device is operative to separate a single quantum particle 824, e.g., electron, etc., from a plurality of particles 822. A single quantum particle is allowed to tunnel (indicated by arrow 810) through the depletion region 808 in an injector mode of operation. An appropriate gate control signal is applied to the gate 806 to establish the energy barrier and to control the tunneling through the depletion region. Note that an appropriate potential might need to be set on doped region 812 prior to this operation. Thus, the interface device functions as an injector tunneling device that allows the tunneling of a single quantum particle, or alternatively a controllable number of particles. When the gate potential is carefully lowered, a single quantum particle (e.g., electron) is allowed to tunnel from the left to the right side of the device.

In addition, in one embodiment, the logical flow of electrons can be provisioned to function in the opposite direction whereby the interface device is part of a circuit that senses and detects the presence of a single particle. In this case, the interface device can serve as the sensor which is coupled to additional classical circuitry (not shown) to detect the presence of single particles. In particular, if the capacitance on the classic side of the device is sufficiently low enough, the presence of a single particle (e.g., electron) on the quantum side of the device can be sensed or detected on the classical side of the device using conventional electronic circuitry, such as 816. This is achieved by detecting the rise in voltage magnitude on the classical side caused by the presence of the single particle on the quantum side upon lowering the barrier of the gate 806. Thus, the interface device is capable of operating bidirectionally as both an injector of a single particle and a detector of a single particle.

Note that in operation, on the classic side of the interface device, the quantum particles, e.g., electrons, are in energy bands, i.e. conduction band and valence band, which enables current flow in classic semiconductor devices. On quantum side of the interface device, the quantum particle is in discrete energy levels with one or two electrons (spin up and down) in each level.

A diagram illustrating a second example interface device of the present invention is shown in FIG. 10B. It is appreciated that the interface device can have many shapes depending on the particular implementation of the invention. In this example, the interface device, generally referenced 830, has an ‘L’ shape and comprises a conventionally low, medium, high, or highly doped region 838 with one or more metal contacts 836, gate 834 and gate contacts 832, and a smaller non-doped (intrinsic) or very low doped region 839 without n+ or p+ doping, contacts, or metal. Note that the ‘L’ shape helps provide shifting on the y-axis and thus increases the distance from other structures.

A diagram illustrating a third example interface device of the present invention is shown in FIG. 10C. In this example, the interface device, generally referenced 840, has a diagonal shape and comprises a conventionally low, medium, high, or highly doped region 848 with one or more metal contacts 846, gate 844 and gate contacts 842, and a smaller non-doped (intrinsic) or very low doped region 849 with n−− or p−− doping.

A diagram illustrating a cross section of a first example semiconductor quantum structure and conventional FET is shown in FIG. 11. The structure, generally referenced 850, comprises a conventional classic FET on the left, a fully quantum device on the right, and a half classic/half quantum interface device in the middle. All three devices are fabricated on substrate 852 and oxide layer 854. It is appreciated that other types of substrates are possible as well.

The classic FET on the left comprises source, drain, and gate including p or n doped well 878, 861 connected to contact 858 and metal 856 structures located on either side of metal or polysilicon (or metal) gate 860 built over oxide layers 851, 853. In classic FET operation, mobile carriers travel from source to drain through inversion channel 855 in accordance with the potential applied to the gate, source and drain terminals. Note that the inversion channel may be pinched wherein carriers are swept by the electric field through the pinched area.

The fully quantum device on the right comprises two qdots in well 879 separated by metal or polysilicon gate 864 and oxide layers 870, 872 over depletion region 868. The gate modulates tunneling (arrow 869) between the two qdots as described in detail supra. Note that the two qdots on either side of gate 864 have no diffusion, contacts or metal.

The half classic/half quantum interface device in the middle comprises metal or polysilicon gate 862 and oxide layers 870, 872 over depletion region 866. The gate modulates tunneling (arrow 867) to allow a single quantum particle to tunnel between doped region 878, 874 on the left side of the gate 862 and the qdot on the right side of the gate. The half classic/half quantum interface structure thus functions to provide an interface mechanism between classic electronic circuitry on the left and quantum circuitry on the right.

A diagram illustrating a cross section of a second example semiconductor quantum structure and conventional FET is shown in FIG. 12. The structure, generally referenced 880, comprises a conventional (i.e. classic) FET on the left, a fully quantum device on the right, and a half classic/half quantum interface device in the middle. All three devices are fabricated on substrate 892 and oxide layer 894.

The classic FET on the left comprises source, drain, and gate including doped well 882, 918 connected to contact 916 and metal 896 structures located on either side of metal or polysilicon gate 898 built over oxide layers 910, 912. In classic FET operation, mobile carriers travel from source to drain through inversion channel 914 in accordance with the potential applied to the gate, source and drain terminals.

The fully quantum device on the right comprises two qdots in well 908 separated by metal or polysilicon gate 900 and oxide layers 902, 904 over depletion region 887. The gate modulates the tunneling (arrow 886) between the two qdots as described in detail supra. Note that the two qdots on either side of gate 900 have no diffusion, contacts or metal.

The half classic/half quantum interface device in the middle comprises metal or polysilicon gate 899 and oxide layers 902, 904 over depletion region 885. The gate modulates the tunneling (arrow 884) between the region on the left of the gate to the region on the right. In this embodiment of the interface device, the doped region 918, 906 of drain of the classic FET is moved closer to the gate 898 and a non-diffusion region is inserted on the left side of the gate 899 in order to reduce parasitic capacitance. The half classic/half quantum interface device functions to provide an interface mechanism between classic electronic circuitry on the left and quantum circuitry on the right.

A diagram illustrating a cross section of a third example semiconductor quantum structure and conventional FET is shown in FIG. 13. The structure, generally referenced 920, comprises a conventional (i.e. classic) FET on the left, a fully quantum device on the right, and a half classic/half quantum interface device (i.e. interface device) in the middle. All three devices are fabricated on substrate 922 and oxide layer 924.

The classic FET on the left comprises source, drain, and gate including doped well 938, 936, 954 connected to contact 928 and metal 926 structures located on either side of metal or polysilicon gate 930 built over oxide layers 942, 944. In classic FET operation, mobile carriers travel from source to drain through inversion channel 940 in accordance with the potential applied to the gate, source and drain terminals.

The fully quantum device on the right comprises two qdots in well 956 separated by metal or polysilicon gate 934 and oxide layers 946, 948 over depletion region 962. The gate modulates tunneling (arrow 964) between the two qdots as described in detail supra. Note that the two qdots 950, 952 on either side of gate 934 have diffusion but no contacts or metal.

The half classic/half quantum interface device in the middle comprises metal or polysilicon gate 932 and oxide layers 946, 948 over depletion region 960. The gate modulates tunneling (arrow 958) between the diffusion region 936, 954 on the left side of the gate 932 and well 956 with diffusion 958 on the right side of the gate. The half classic/half quantum interface device functions to provide an interface mechanism between classic electronic circuitry on the left and quantum circuitry on the right. Note that in one embodiment, similar structures can be built using bulk processes with no oxide layer under the quantum structure but with a depletion region instead.

As described supra, the quantum processor of the present invention comprises a mix of structures including quantum structures, conventional/classic FET structures, and interface devices comprising half classic and half quantum operation which are used to move information from the conventional FET (i.e. non-quantum) domain to the full quantum domain.

A diagram illustrating an example quantum structure with interface devices is shown in FIG. 14. The example structure, generally referenced 670, comprises a middle full quantum structure (dashed circle 683) having gate 689 sandwiched by a left side interface device structure (dashed circle 681) with gate 674 and a right side interface device structure (dashed circle 685) with gate 676. The interface devices 681, 685 comprise a conventional FET (darkened areas 684, 687) on one side of their gate and quantum device on the other side.

The structure 670 comprises two qdots and utilizes well-to-well tunneling through local depleted region. An interface device is located at each end for interfacing with conventional electronic circuits. The potential on the control gate can be applied either with a direct voltage drive network or via a floating impedance division. The well is realized with two rectangular wells having an overlap to create the narrow tunneling channel 671.

A diagram illustrating a first example multiple qdot quantum structure with interface devices on either end thereof is shown in FIG. 15A. The higher complexity semiconductor quantum structure, generally referenced 690, comprises a continuous well with a plurality of imposing control gates 696 and gate contacts 692 that separate it into a plurality of qdots 698. In this example, the well comprises a plurality of overlapping squares connected at their corners to create a narrow tunnel path 699. Located at either ends of the well are interface devices 694 that allow the connection of the reset, injection and detection circuits. The imposer gates 696 receive pulsed control signals that determine the specified quantum operation.

A diagram illustrating a CAD layout of an example quantum structure is shown in FIG. 15B. The layout, generally referenced 700, comprises a continuous well with a plurality of control gates 706 and gate contacts 704 that form a plurality of qdots 702. In this example, the well comprises a plurality of abutting squares connected at their edges to create a tunnel path. Located at either ends of the well are interface devices 708 with contacts 709 that allow the connection of the reset, injection and detection circuits (not shown). Note that these three circuits can be all electrically connected to the same node, for example, 812 in FIG. 10A.

A diagram illustrating a cross section of the quantum structure of FIG. 15A is shown in FIG. 16. The quantum structure has multiple qdots with interface devices at both ends of the well. The single continuously drawn well is separated into a plurality of qdots by the local depletion regions induced by a plurality of control gates. The cross section 710 comprises a substrate 712 and oxide layer 714 on which are fabricated seven qdots 722 comprising six control gates 722 each including oxide layers 728, 730, and polysilicon or metal layer 726, two interface devices 720 each including n or p doped regions 718, 716, contact 711, and metal layer 713, and gate 732.

To illustrate the operation of the quantum structure of the present invention, a series of diagrams are presented that show the steps involved in an example quantum operation starting with a single quantum particle where the local depletion region is under control of the gate.

A diagram illustrating the aperture tunnel barrier for a two quantum dot structure is shown in FIG. 17A. The local depletion region under the control gate divides the structure into two qdots, namely a left qdot storage 741 and a right qdot storage 743. The tunnel barrier imposed by the local depletion region is represented by trace 740. In this phase, the depletion region is wide and the tunnel barrier is high (referenced 742) and the particle 746 cannot tunnel to the right qdot storage and is trapped in the left qdot storage.

A diagram illustrating a first example change in the aperture tunnel barrier for the two quantum dot structure is shown in FIG. 17B. The tunnel barrier imposed by the local depletion region is represented by trace 744. In this phase, an appropriate potential is applied to the control gate to cause the depletion region to narrow thus lowering the tunnel barrier (referenced 745). This permits the particle 748 to travel to the right qdot storage and the particle is in the left and right qdots at the same time.

A diagram illustrating a second example change in the aperture tunnel barrier for the two quantum dot structure is shown in FIG. 17C. The tunnel barrier imposed by the local depletion region is represented by trace 750. In this phase, the potential applied to the control gate is adjusted to cause the depletion region to widen again thus raising the tunnel barrier (referenced 752). This effectively traps the two split particles 747, 748 (i.e. the wavefunction of the particle is split) and prevents them from traveling from one qdot to the other through the tunnel barrier. In quantum fashion, the charge carrier is split between the two qdots. When performing detection, however, the carrier will only be on one side with a corresponding probability.

Thus far only electric control of semiconductor quantum structures has been presented wherein the spin of the quantum particle is ignored. An alternative manner of controlling the semiconductor quantum structure is to control/select the spin of the quantum particle using a magnetic field from an inductor/coil or a resonator. A property of particles is that they tend to align their spins to any external relatively strong magnetic field. A diagram illustrating an example quantum structure surrounded by a spin control magnetic coil is shown in FIG. 18.

The structure, generally referenced 760, comprises a resonator 763 or one or more turns of a coil 762 surrounding a continuous well divided into two qdots 764 by control gate 766 and connected by tunnel path 768. Along with the electrical control of the imposing gate, this structure also uses the magnetic field generated either by (1) an inductor 762 or (2) a resonator 763 that surrounds the entire quantum structure to select the spin of the particle. Note that both are shown in the figure but in practice typically only one is implemented. Note also that both static and ac magnetic fields can be generated and used. In addition, the inductor may overlap only a local area including one or several quantum structures or it can overlap the global area where the quantum core is implemented. In this manner, local magnetic control or global magnetic control can be implemented.

As described supra, the quantum computer operating environment employs cooling at cryogenic temperatures. In addition, electric and magnetic field shielding is provided. The cryostats used typically comprise relatively large metal structures that act as good shields. In one embodiment, the metal cavity of the cryostat creates a high quality resonator that generates a magnetic field to control the semiconductor quantum structures at its interior.

A diagram illustrating a second example multiple qdot quantum structure is shown in FIG. 19. The structure, generally referenced, 770, comprises a blended continuous well path 772 overlapped by a plurality of control gates 776 with contacts 774 (three in this example). Here the width of the vertical segments of the control gates and the vertical and horizontal segments of the well are the same, i.e. a “boomerang” structure in which the width of the wider well regions is made equal to the width of the narrow channel links. Such a structure results in a more compact realization of the quantum structure. Note that the regions between control gates form the quantum dots, while the regions under the control gates realize the induced depletion regions through which tunneling occurs. It is appreciated that any number of qdot structures can be realized depending on the number of control gates implemented. Note that in one embodiment, such structures can be implemented using either planar or 3D semiconductor processes.

A diagram illustrating a third example multiple qdot quantum structure is shown in FIG. 20. In an alternative embodiment, the semiconductor structure comprises a bended well path overlapped by gates using horizontal and inclined well segments. Note that vertical segments also possible. In particular, the structure, generally referenced, 780, comprises a blended continuous well path 782 overlapped by a plurality of control gates 786 with contacts 784 (three in this example) using horizontal and inclined well segments. Here too the width of the vertical segments of the control gates and the vertical and horizontal segments of the well are the same, i.e. a “boomerang” structure in which the width of the wider well regions is made equal to the width of the narrow channel links. Such a structure results in a more compact realization of the quantum structure. Note that the regions between control gates form the quantum dots, while the regions under the control gates realize the induced depletion regions through which tunneling occurs. It is appreciated that any number of qdot structures can be realized depending on the number of control gates implemented.

A diagram illustrating a fourth example multiple qdot quantum structure is shown in FIG. 21. In an alternative embodiment, the semiconductor structure comprises a bended well path overlapped by gates using horizontal and rounded well segments. Note that vertical segments also possible. In particular, the structure, generally referenced, 790, comprises a blended continuous well path 792 overlapped by a plurality of control gates 796 with contacts 794 (three in this example) using horizontal and rounded well segments. Note that the regions between control gates form the quantum dots, while the regions under the control gates realize the induced depletion regions through which tunneling occurs. It is appreciated that any number of qdot structures can be realized depending on the number of control gates implemented.

Quantum State Detection

In semiconductor quantum structures and circuits, the qubits (i.e. elementary quantum information units) are encoded by the state of particles or carriers inside one or more semiconductor layers. To help to achieve the single carrier behavior, the semiconductor layers are usually fully depleted. In the case of spin qubits the detection includes determining the spin orientation of a given carrier (e.g., electron or hole), while in the case of charge qubits (i.e. position qubits) the detection includes determining if the carrier is present or not in a given qdot.

Classically, a bit can have only two values “0” and “1”. In the quantum domain, however, a qubit can have a large number of values given by any constrained combination of the two base quantum states |0> and |1>. This is provided by the superposition character of the quantum states.

When a quantum state is detected, the quantum state is collapsed into a base state which corresponds to a classic state with a given probability associated with it. For example, in the detection of a charge qubit, the outcome can be either: (1) the carrier is present in the detection qdot which corresponds to the base state |1>; or (2) the carrier is not present in the detection qdot which corresponds to the base state |0>. To determine the value of a quantum state, a number of successive quantum experiments are performed to get the average presence probability of the detected carrier. By computing the number of |0>s and |1>s that are obtained in the detection, the probability of the quantum state is determined.

For example, consider the Hadamard equal distribution quantum state denoted by 0.707|0>+0.707|1> where the carrier is split equally into two qdots of the quantum gate. From the quantum perspective, this means the carrier is present simultaneously in both qdots. In the classic view, the electron cannot be split and it either is present in a given qdot or it is absent from that qdot. When detecting a Hadamard state multiple times it is expected to obtain an equal number of collapses to the |0> base state (i.e. the carrier is absent) and to the |1> base state (i.e. the carrier is present) in the detected qdot. If the quantum state has a given rotation and it has a larger |1> base state component (a|0>+b|1> with b>a) then at detection more collapses to the base state |1> should occur. If in contrast, the quantum state has a rotation towards the |0> base state (a|0>+b|1> with a>b) then more collapses to the base state |0> should occur.

In order to perform detection of a quantum state contained in a quantum device, the quantum structure is connected to classic devices. This is achieved using an interface device, described in detail supra. Such interface devices are half-quantum and half-classic in their nature or interpretation. In one embodiment, the detector circuit itself comprises classic devices that process charge, current, and voltage. The quantum devices operate with single carrier (e.g., electron or hole), or a small controllable number thereof, while the interface device extracts a single carrier from a sea of collective electrons in the classic world or vice versa injects a single carrier into a classic world sea of collective carriers.

In one embodiment, the classic device of the detector is connected at a quantum structure using a floating well, in which the interface device has a quantum well on one side and a floating classic well on the other. Since the classic well is set to be floating, the injection of a single carrier may result in a noticeable well potential change that can be amplified further.

In another embodiment, the classic device of the detector is connected at a quantum structure using floating gate detection. In this case, the interface device is realized by a device having a plurality of gates, one of them being shared with a classic FET detector device. When the carrier arrives under the floating gate of the interface device it changes the potential of the gate, which in turn can be measured by the classic FET of the detector which shares the gate with the interface device.

Floating Well Detection

In floating well detection, the quantum particle is injected from the quantum device (if it happens to be present there) into a classic floating well that is in turn connected to the input of the classic detector circuit. An equivalent schematic of the quantum circuit, generally referenced 990, together with its associated interface and classic circuits is shown in FIG. 22A. A top plan layout view of the circuit is shown in FIG. 22B and a cross section of the circuit is shown in FIG. 22C. The quantum circuit 990 comprises several layers including substrate 1010, BOX oxide 1008, and undoped fully depleted layer 1006. Doped regions 1020 are fabricated over the fully depleted layer.

In one embodiment, before starting a quantum operation, the entire quantum structure is reset, i.e. the entire quantum well is flushed of any free carriers. Since the quantum well is fully depleted, there are no carriers in it. A reset operation is performed by one or more classic Mreset devices 992 by appropriately controlling the interface quantum gates (Qinterface) 994 and imposer quantum gates (Qimp) 996. The classic Mreset device comprises metal contacts 1002 on its terminals realized by doped semiconductor layers 1020. Considering the SOI semiconductor process as an example, the source and drain doped diffusions are fabricated above the undoped fully depleted device body 1006. The Mreset device establishes a reference potential for the classic side of the classic to quantum interface device on the left. During the quantum operation it is assumed that this potential does not change much due to leakage currents.

In one embodiment, quantum operation begins by initially resetting the classic well to a reference potential then setting it floating during the detection time interval. A single carrier (e.g., electron or hole, if one happens to be present there) is injected from a classic well 1022 where a sea of carriers have a collective behavior, into a quantum well 1024 where single carrier behavior can occur. An appropriate potential is applied to the gate 1004 of the Qinterface device 994 to control the tunneling of a single particle 1012 to the quantum side by lowering the tunneling barrier. Once the single particle is injected into the fully depleted well 1024, it moves according to the potential distribution change determined by the plurality of quantum imposing gates (Qimp) 996. In one embodiment, the Qimp gates determine the creation of valleys in the potential distribution that is progressively shifted from left to right and thus determine the movement of the particle 1012. Depending on the timing and pulse widths of the Qimp signals, a carrier may be split between different locations in the fully depleted well in which two or more potential valleys may be realized. This is the base of generating the superposition quantum states (a|0>+b|1>).

At the opposite end of the well, a second interface device 998 provides the interface in the other direction from the quantum well 1026 to the classic well 1014. In one embodiment, the classic well is left floating (no dc path to ground) such that the potential injection or transfer (by virtue of the connecting transistor 998) of a single carrier can generate a measurable change in potential that is further processed by the detector classic circuit 1000. Since the particle is injected (or transferred) from the quantum well into a classic well, the quantum state collapses. This detection is destructive since the quantum state is destroyed during the measurement process. It is destroyed specifically during the instance the particle sees a low resistance path, i.e. is connected, to the sea of carriers on the classic side. It is noted that such destructive detection can be performed only once per quantum operation. Furthermore, it is noted that another reset device similar to 992 can be connected to the same node 1014 as that connected to the detector 1000. Likewise another detector similar to 1000 can be connected to the reset device 992 (node 1003). These two types of circuits operate in a time shared manner in which the active time slots allocated to them can be different. Their high resistance during the inactive time slots ensures no conflicts.

The floating classic well 1014 is connected to the gate 1016 of a detection device 1000. The floating well and the gate 1016 of the detector Mdetector have a certain total capacitance. The voltage change in the signal at the gate 1016 of Mdetector is given by ΔV=e/C where e is the carrier charge 1.6×10⁻¹⁹ Coulomb and C is the total capacitance of the floating well (1014 and possible 1026) and gate. In one embodiment, the charge to voltage conversion is followed by classic voltage or transconductance amplifiers depending on the voltage mode or current mode operation of the classic detector circuit 1000. Note that the entire single carrier (e.g., electron) injection, quantum processing/imposing and detection is short in comparison with the decoherence time of the particle in the given semiconductor structure.

Note that other classic analog, mixed signal or digital circuits are preferably kept an exclusion distance away from the quantum structure 990 in order to avoid undesired parasitic interaction with the quantum particle(s) that could lead to quantum decoherence.

Floating Gate Detection

The second option for the detection of the quantum state is to use a floating gate. In this case the classic device of the detector Mdetector is connected to the same floating gate that goes over the quantum well. An equivalent schematic of the quantum circuit, generally referenced 1030, together with its associated interface and classic circuits is shown in FIG. 23A. A top plan layout view of the circuit is shown in FIG. 23B and a cross section of the circuit is shown in FIG. 23C. The quantum circuit 1030 comprises several layers including substrate 1050, BOX oxide 1048, and undoped fully depleted layer 1046. Doped regions 1058 are fabricated over the fully depleted layer.

Similar to the floating well detection circuit 990 described supra, the quantum procedure starts with the reset of the structure 1030 using one or more classic Mreset devices 1032 along with appropriate control of the interface quantum gates (Qinterface) 1034 and imposer quantum gates (Qimp) 1036 such that all free carriers in the quantum structure are flushed out. The classic to quantum Qinterface device 1034, operative to inject a single carrier 1052 into the quantum structure, has a half-classic and half-quantum operation. It comprises a doped and metal contacted classic well 1054 on the left side of its gate 1044 and a floating quantum well 1056 on the other side. In one embodiment, the connection between the Mreset and Qinterface devices on the classic side is realized with contacts and metal layers 1055. Note that the Mreset and Qinterface devices may share the same active layer or may be done in separate active layers.

The quantum imposer (Qimp) devices 1036 determine the specific quantum computation performed. There is at least one Qimp quantum control gate. Alternatively, the circuit may comprise any number of Qimp devices as large as feasible in the actual implementation using a given semiconductor process.

The last three gates over the quantum well on the right side of the circuit 1030 form a quantum to classic Qinterface device 1038, 1064, 1062. Note that alternatively, the Qinterface device may be located in the middle of a quantum well. One of the three gates (1060) is the floating gate which connects to the Mdetector classic detector device 1040. In one embodiment, the carrier is moved under the floating gate by controlling the potential distribution with the two adjacent gates 1059, 1061. The presence of the quantum carrier under the floating gate causes a change of the potential of the quantum gate which is sensed by the Mdetector detector device 1040 and amplified further.

After the first measurement is performed, the quantum carrier can be moved away from under the floating gate 1060 of the interface device. The floating gate initial potential is set during the reset time to a level that allows the proper operation of the Mdetector classic detector device. Such potential may be reset for example with a second classic Mreset device (not shown) connected to the gate of the Mdetector device.

An example potential diagram for the floating gate detection circuit is shown in FIG. 24. The last quantum imposer gate Qimp 1076 together with the three gates 1077, 1078, 1079 of the quantum to classic interface device (Qinterface) 1070 are shown. In this example, two of the three gates (left gate 1077 and right gate 1079) are controlled and not floating while only the middle gate 1078 is floating. The middle floating gate 1078 is connected to the detector circuit 1040 (FIG. 23A). It is appreciated that the Qinterface device may comprise more or less than three gates. For example, the detection can be performed using only two interface device gates, i.e. one floating and one controlled.

In operation, the particle is moved one or more times under the floating gate to perform detection (i.e. nondestructive measurement). Multiple measurements are performed under the detection gate for the same quantum experiment. A measurement is made each time the particle moves under the floating gate 1078. Note that the movement is speculative in nature since it is not known a priori whether there is a particle present or not as this is what is being measured. If no particle is detected, then of course no movement actually takes place. Potential diagram (A) shows the quantum particle (e.g., carrier, electron, hole, etc.) 1072 stuck in the last quantum dot by the last Qimp control quantum gate 1076. By controlling the left 1077 and right 1079 interface device gates the potential in the fully depleted well 1046 underneath them can be modified such that a wide valley 1080 is realized which extends under the floating gate in the middle of the quantum to classic interface device, as shown in potential diagram (B). In this case, the particle extends in the entire area allowed by the potential valley 1080. In the next step, the control gates modify the potential distribution so that the potential valley extends only under the floating gate 1078, as shown in potential diagram (C). Having the particle located directly under the floating gate generates a change in potential of the floating gate which can be measured and amplified by the Mdetector circuit 1040 (FIG. 23A) using one or multiple classic FET devices.

Lowering the potential of the left gate 1077 while raising the potential of the right gate 1079 extends the valley as shown in potential diagram (D). In potential diagram (E), the valley is restricted and the particle moves to the right away from the floating gate in potential diagram (F), the interface device gates are configured to widen the potential valley that extends under both the floating gate and the right interface gate 1079. The carrier again will occupy all the space of the valley. In the next step shown in potential diagram (G), the control gates of the interface device are configured to change the potential such that the carrier moves under the floating gate where a new measurement can be performed. In such case the potential of the floating gate will change in an opposite direction.

In potential diagram (H), the control gates are configured to widen the potential valley to include the area under the floating gate and in potential diagram (I), the potential valley is restricted again.

Note that an advantage of the floating gate detection mechanism is that it is not destructive and the carrier's wavefunction does not collapse in the detection process. This allows the detection of the quantum particle multiple times. Therefore, instead of performing the entire quantum experiment multiple times, the quantum experiment is performed once but the results are measured multiple times. This provides for a faster total quantum cycle and helps to increase the fidelity of the quantum operation.

In another embodiment, the floating gate detection may be followed by a floating well detection which finally collapses the quantum state. By using both methods of detection, a more sophisticated detection scheme can be built with lower error rate. By looking at the correlation between the two types of detection, built-in detection error correction can be realized.

3D Semiconductor Quantum Structures

The present invention provides a semiconductor quantum structure that uses a 3D semiconductor process with very thin semiconductor fins having much smaller parasitic capacitance to the gate. This results in higher Coulomb blockade voltages and thus quantum circuits that are easier to control with classic electronic circuits with more noise floor margin. Two semiconductor islands are isolated in a continuously drawn fin using an overlapping control gate that induces a local depletion region in the fin. The tunneling between one island in the fin to the other is controlled by the control gate that imposes the potential on the fin. By modulating the potential applied to the control gate, a controlled fin-to-fin tunneling through the local depletion region is achieved, realizing the function of a position/charge qubit. More complex structures with higher number of qdots per continuous fin and larger number of fins can be constructed. 3D semiconductor processes can be used to build such fin-to-fin tunneling quantum structures. Hybrid 3D and planar structures can be built as well. By combining a number of such elementary quantum structures a quantum computing machine is realized.

A diagram illustrating an example 3D semiconductor quantum structure using fin to fin tunneling through local depletion region is shown in FIG. 25. The quantum structure, generally referenced 1840, comprises a continuously drawn fin 1846, overlapping control gate 1843, two isolated semiconductor well and fin structures realize qdots #1 and #2 1842, local depletion region 1848, tunneling path 1841, and particle, e.g., electron or hole, 1844. A diagram illustrating a three dimensional view of an example 3D semiconductor quantum structure with fin to fin tunneling under control of a control gate is shown in FIG. 26. The quantum structure, generally referenced 1850, comprises fins with portions 1851, 1853, overlapping control gate 1854, substrate 1855, and local depletion region 1852. Note that the well may be omitted and the qdot realized by the semiconductor fin area only.

With reference to FIGS. 25 and 26, the control gate layer overlaps the fin on three sides and creates a local depleted region which isolates the two sides when the potential barrier is high. Note that overlapping the fin provides better control over the structure. A thin oxide layer separates the semiconductor fin from the control gate. When the control terminal lowers the potential barrier, tunneling can occur from one side of the fin to the other side. The tunneling is controlled by the control terminal that imposes the potential in the semiconductor fin. If the tunnel barrier is high, the quantum particle is locked in its prior state. When the potential on the control terminal lowers the barrier, the quantum particle can tunnel from one qdot to the other. Depending on the pulse width of the control signal, the quantum particle completely or partially tunnels. In the latter case, the quantum particle (precisely, its wavefunction) is distributed between the two qdots, i.e. spatial entanglement. Note that in real implementations, the quantum structure generally has a deformed complex 3D shape where the depletion region depends on the particular implementation and semiconductor process used. The structures shown herein are for illustration purposes only.

A diagram illustrating a cross section, side view, and top view of an example 3D two qdot quantum structure using local fin depletion tunneling is shown in FIG. 27A. The quantum structure, generally referenced 1860, comprises substrate 1869, optional oxide layer 1861, wells 1862, 1865, fin 1863, gate oxide 1866, and overlapping control gate 1864. Note that the dotted line indicates the optional oxide layer that isolates the 3D quantum structure from the substrate. The substrate may comprise standard resistivity, high resistivity, or isolating substrates.

The tunneling through a local depletion region in the quantum structure is induced in a fin by the overlapping control gate. When the barrier is high, the local depleted region is wide and virtually no tunneling current is allowed. When the barrier is lowered, the local depleted region shrinks in width and a sizeable leakage tunneling current appears, which allows the particle to move from one qdot to the other. If the particle has not completed the move from one qdot to the other, it will spread (equally or non-equally) between the two qdots to achieve spatial particle entanglement.

A diagram illustrating a cross section, side views, and top view of an example 3D multiple qdot quantum structure using local fin depletion tunneling is shown in FIG. 27B. The quantum structure, generally referenced 1870, comprises substrate 1879, optional oxide layer 1871, wells 1872, 1876, fin 1873, gate oxide 1877, and overlapping control gates 1874, 1875. Note that the dotted line indicates the optional oxide layer that isolates the 3D quantum structure from the substrate. The substrate may comprise standard resistivity, high resistivity, or isolating substrates. The quantum structure 1870 is useful when quantum transport is needed, i.e. quantum shift and particle spatial entanglement, and can be realized in bulk 3D semiconductor processes, e.g., FinFET, or in SOI 3D semiconductor processes.

A diagram illustrating two example double V fin-gate-fin structures having two wells placed in close proximity allowing quantum particles to interact is shown in FIG. 28A. The quantum interaction gate, generally referenced 1880, comprises two 3D structures comprising a plurality of qdots 1882, 1888, fins 1884, control gates 1886, and interaction qdots 1881.

In this embodiment, the inner two semiconductor wells 1881 come in very close proximity thereby allowing a strong interaction between particles or distributed particles in the two qdots. The distance between other pairs of qdots is significantly larger and thus the interaction between corresponding particles is much smaller, ideally negligible. In this manner, the double V quantum structure shifts two or more particles into specific positions for a well controlled interaction and then transports them apart. The preparation of the quantum state also happens when particles are further away and thus can be done largely independent one from the other. This also allows a well-controlled interaction between particles only when they are in specific qdots and when the control signals are configured to enable the interaction.

A diagram illustrating an example 3D semiconductor quantum structure using fin-to-fin tunneling through a local depleted region with a shared well between two fin paths providing bifurcation is shown in FIG. 28B. The quantum structure, generally referenced 1890, comprises a plurality of qdots 1892, namely qdots #1, #2, #3, #4, fins 1896, and control gates 1894. The well of qdot #2 1898 overlaps two fins to provide path bifurcation whereby particles can move between qdots #1 and #4 and between qdots #3 and #4.

Note that this quantum structure can realize either a bifurcation of the quantum operation path or a merger of the quantum operation path. This structure is useful in creating more complex quantum structures. Note also that the control gates overlapping the two fins and separating qdots #1 and #3 can be separated (as shown) or can be shared (not shown).

A diagram illustrating an example quantum structure with dummy gates and gate cuts that separate control and dummy gates is shown in FIG. 28C. The quantum structure, generally referenced 1900, comprises qdots 1902, namely qdots #1 to #6, fins 1904, control gates 1901, contacts 1903, dummy gates 1906 not used in operation of the circuit, and gate cuts 1908. Depending on the actual 3D semiconductor process used, dummy gates may be needed but they remain floating with no potential. The gates need to be equally spaced and on the edges of the well. In addition, they may need to be cut in order to prevent unwanted interactions. The cutting may be done on top of a dummy fin, or alternatively without the fin. Although 12 control gates are shown, only four are active.

A diagram illustrating an example hybrid planar and 3D semiconductor quantum structure using both fin-to-fin and well-to-well tunneling through local depletion region is shown in FIG. 28D. The quantum structure, generally referenced 1910, comprises 3D qdots 1912, fins with portions 1914, 1913, 3D control gate 1918, planar qdots 1911, and planar control gate 1916. This hybrid embodiment uses both 3D and planar tunneling structures which is possible in a 3D semiconductor process. The inner quantum structure is planar with two overlapping wells (i.e. qdots) and uses well-to-well tunneling through a local depletion region. The outer, i.e. left and right, quantum structures are 3D and use fin-to-fin tunneling through a local depletion region. Note that the two types of tunneling have different barrier levels and thus require different control gate signals.

The present invention also provides a semiconductor quantum structure that uses a 3D semiconductor process used to fabricate two semiconductor fins and an overlapping imposing control gate that constitutes the tunneling path from one semiconductor qdot to the other. The tunneling is controlled by the control gate that imposes the potential on the tunneling path. By modulating the potential of the imposer gate, a controlled fin-gate and gate-fin tunneling through the thin oxide under the control gate is enabled, realizing the function of a position/charge qubit. More complex structures with higher number of qdots per continuous well and larger number of wells can be built. Both planar and 3D semiconductor processes can be used to build well/fin-to-gate and gate-to-fin/well tunneling quantum structures. Hybrid 3D and planar structures can be built as well. By combining a number of such elementary quantum structures a quantum computing machine is realized.

A diagram illustrating an example 3D semiconductor quantum structure using fin-to-gate tunneling through oxide is shown in FIG. 29. The quantum structure, generally referenced 1920, comprises two wells 1921, 1927 with fin structures 1923, 1926 to realize the quantum dots #1 and #2, a gate layer with oxide 1924 overlaps both fins and creates a tunneling path from one fin to the other. A diagram illustrating a three dimensional view of an example 3D semiconductor quantum structure using fin-to-gate and gate-to-fin tunneling through oxide is shown in FIG. 30. The quantum structure, generally referenced 1930, comprises fins 1932, 1938, overlapping control gate with oxide layer 1936, substrate 1931, and local depletion region 1934. Note that the well may be omitted and the qdot realized by the semiconductor fin area only.

With reference to FIGS. 29 and 30, the tunneling is controlled by the control terminal that imposes the potential on the tunneling gate. In one embodiment, the control gate is substantially floating but it is electrostatically coupled to the control terminal nearby (not shown). If the tunnel barrier is high, the quantum particle is locked in its prior state. When the control terminal determines a lowering of the barrier, the quantum particle is allowed to tunnel from one qdot to the other. Depending on the pulse width of the control signal, the quantum particle either completely or partially tunnels through. In the latter case, the quantum particle is distributed between two qdots to achieve a spatial superposition state. A thin oxide layer separates the semiconductor fin from the control gate. Note that in real implementations, the quantum structure generally has a deformed complex 3D shape where the depletion region depends on the particular implementation and semiconductor process used. The structures shown herein are for illustration purposes only.

A diagram illustrating a cross section, side view, and top view of an example 3D semiconductor quantum structure using fin-to-gate tunneling through oxide is shown in FIG. 31. The quantum structure, generally referenced 1950, comprises substrate 1951, optional oxide layer 1957, wells 1952, fins 1953, 1955, gate oxide 1956, and overlapping control gate 1954. Note that the dotted line indicates the optional oxide layer that isolates the 3D quantum structure from the substrate, i.e. SOI process. The substrate may comprise standard resistivity, high resistivity, or isolating substrates.

The tunneling through the oxide in the quantum structure is induced in a fin by the overlapping control gate. When the barrier is high, virtually no tunneling current is allowed. When the barrier is lowered, tunneling through the gate oxide allows the particle to move from one qdot to the other. If the particle has not completed the move from one qdot to the other, it will spread (equally or non-equally) between two qdots to achieve a superposition state.

A diagram illustrating a cross section of an example 3D semiconductor quantum structure using fin-to-gate and gate-to-fin tunneling is shown in FIG. 32. The quantum structure, generally referenced 1940, comprises substrate 1941, optional oxide layer 1942, fins 1945, 1946, gate oxide 1944, and overlapping control gate 1943. As described supra, the tunneling through the oxide layer 1944 is controlled by the overlapping control terminal that imposes the potential on the control gate. If the tunnel barrier is high, the quantum particle is locked in its prior state. When the control terminal determines a lowering of the barrier, the quantum particle is allowed to tunnel from one qdot to the other.

A diagram illustrating a top view of an example two qdot 3D semiconductor quantum structure using fin-to-gate tunneling through oxide is shown in FIG. 33. The quantum structure, generally referenced 1990, comprises two wells 1992, 1996 with fin structures 1993 that realize quantum dots #1 and #2 and a control gate layer with oxide 1994 overlapping both fins creating a tunneling path 1995 for particle 1992 from one fin to the other.

Note that different shapes can be used for the layers used to construct the quantum structure, e.g., squares, rectangles, polygons, circles, composed shapes, etc. as described supra. In this embodiment, two wells are added, one to each fin which crosses the well in the middle. When the control terminal lowers the barrier, the quantum particle in the left qdot tunnels to the right qdot.

A diagram illustrating an example double V quantum interaction structure using 3D semiconductor process with fin-to-gate tunneling is shown in FIG. 34A. The quantum interaction gate, generally referenced 1960, comprises two 3D structures comprising a plurality of qdots 1964, fins 1968, control gates 1966, and interaction qdots 1962.

In this embodiment, the inner two semiconductor wells 1962 come in very close proximity thereby allowing a strong interaction between particles or distributed particles in the two qdots. The distance between other pairs of qdots is significantly larger and thus the interaction between corresponding particles is much smaller, ideally negligible. In this manner, the double V quantum structure shifts two or more particles into specific positions for a well controlled interaction and them transports them apart. The preparation of the quantum state also happens when particles are further away and thus can be done largely independent one from the other. This also allows a well controlled interaction between particles only when they are in specific qdots and when the control signals are configured to enable the interaction.

A diagram illustrating an example quantum structure with fin-to-gate tunneling with dummy gates and cuts to create dummy fins is shown in FIG. 34B. The quantum structure, generally referenced 1970, comprises a plurality of qdots 1972, fins 1973, control gates 1974, contacts 1975, dummy gates 1971 not used in operation of the circuit, and gate cuts 1976. Depending on the actual 3D semiconductor process used, dummy gates may be needed which remain floating with no potential. The gates need to be equally spaced and on the edges of the well. In addition, they may need to be cut in order to prevent unwanted interactions. The cutting may be done on top of a dummy fin, or alternatively without the fin.

A diagram illustrating an example hybrid planar and 3D semiconductor quantum structure using both fin-to-gate and well-to-gate tunneling is shown in FIG. 34C. The quantum structure, generally referenced 1980, comprises 3D qdots 1982, fins 1984, 1986, 3D control gate 1986, planar qdots 1988, and planar control gate 1989. This hybrid embodiment uses both 3D and planar tunneling structures which is possible in a 3D semiconductor process. The inner quantum structure is planar with two wells (i.e. qdots) and uses well-to-gate tunneling through oxide. The outer, i.e. left and right, quantum structures are 3D and use fin-to-fin tunneling through oxide. Note that the two types of tunneling have different barrier levels and thus require different control gate signals.

Those skilled in the art will recognize that the boundaries between logic and circuit blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures may be implemented which achieve the same functionality.

Any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality may be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermediary components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.

Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first,” “second,” etc. are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. As numerous modifications and changes will readily occur to those skilled in the art, it is intended that the invention not be limited to the limited number of embodiments described herein. Accordingly, it will be appreciated that all suitable variations, modifications and equivalents may be resorted to, falling within the spirit and scope of the present invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. 

What is claimed is:
 1. An interface device for interfacing between classic field effect transistor (FET) circuitry and quantum circuitry, comprising: a substrate; a first substantially undoped or low-doped well constructed on said substrate in which both a classic well and a quantum well are realized; a first doped diffusion in or above said first well forming a classic well constituting a classic side of said device; a control gate constructed over at least a portion of said first well wherein a potential applied to said control gate is operative to control a tunneling path thereunder; and a second well formed by a remainder of said first well on an opposite side of said control gate forming a quantum well constituting a quantum side of said device.
 2. The interface device according to claim 1, wherein the potential applied to said control gate determines a transport of a single carrier from said classic well to said quantum well.
 3. The interface device according to claim 1, wherein the potential applied to said control gate determines a transport of a single carrier from said quantum well to said classic well.
 4. The interface device according to claim 1, wherein a potential of said classic well is set to a given reference value through a reset process and the potential of said control gate is modified with respect to the reference value to establish transport of a single carrier from said classic well to said quantum well.
 5. The interface device according to claim 1, wherein an interface device is located at one or both ends of a continuous substantially undoped well.
 6. The interface device according to claim 1, wherein said substrate is selected from a group comprising a semiconductor, silicon on insulator (SOI), insulating substrate replacement, and a bulk substrate having a global depletion layer that isolates top devices from said substrate.
 7. The interface device according to claim 1, wherein said first doped diffusion is selected from a group consisting of low doped (n−, p−), medium doped (n, p), high doped (n+, p+), and highly doped (n++, p++) and said second well is selected from a group consisting of intrinsic undoped, and very low doped (n−−, p−−).
 8. The interface device according to claim 1, wherein first doped diffusion and said second well have a shape selected from a group consisting of: a circle, an ellipse, a square, a rectangle, a trapezoid, two squares diagonally connected at their corners, two rectangles diagonally connected at their corners, two squares overlapping at their corners, two rectangles overlapping at their corners, two squares connected at their corners to a third smaller square, two squares connected at their corners to a smaller double square, two rectangles connected at their corners to a third smaller square, two rectangles connected at their corners to a smaller double square, two diagonally overlapping squares connected at a corner to another two diagonally overlapping squares, two diagonally overlapping rectangles connected at a corner to another two diagonally overlapping rectangles, a path at an inclined angle from the orthogonal axis, a path at 45 degrees from one of the orthogonal axis, and any combination thereof.
 9. The interface device according to claim 1, wherein said first doped diffusion is aligned with an edge of said control gate.
 10. The interface device according to claim 1, wherein second well extends beyond an edge of said control gate on the classic side and the doped diffusion is at a certain distance from the edge of said control gate.
 11. The interface device according to claim 1, wherein said control gate is selected from a group comprising a contacted control gate directly driven by an electronic signal, metal gate or well imposed floating control gate utilizing adjacent or overlapping positioning, and a floating control gate with an imposing adjacent gate potential.
 12. The interface device according to claim 1, wherein said second well is surrounded by oxide, one or more insulating layers, and/or one or more wide depletion regions.
 13. The interface device according to claim 1, wherein the potential applied to said control gate comprises one or more pulses signal having two or more controlled amplitude levels, controlled time duration, and controlled transition times.
 14. The interface device according to claim 1, wherein an appropriate potential applied to said control gate enables a single quantum particle to tunnel from said classic side to said quantum side of said device in an injector mode of operation.
 15. The interface device according to claim 1, wherein a single quantum particle is transported from said quantum well to said classic well where its presence is detected by a detector circuit coupled to said classic well.
 16. An interface device for interfacing between classic field effect transistor (FET) circuitry and quantum circuitry, comprising: a substrate; a first well constructed on said substrate and substantially doped in accordance with a classic FET device to form a classic side; a contact layer operative to establish an electric connection between a metal layer going to other classic devices and said first well; a second well constructed on said substrate and substantially undoped in accordance with a quantum structure to form a quantum side; a control gate fabricated to overlap at least a portion of said second well; and wherein application of an appropriate potential to said control gate enables tunneling of a single quantum particle through a local depleted tunneling path between said first well and said second well.
 17. The interface device according to claim 16, wherein the tunneling of a single quantum particle has the direction from said classic side to said quantum side of said device in an injection mode of operation.
 18. The interface device according to claim 16, wherein the tunneling of a single quantum particle has the direction from said quantum side to said classic side of said device in a detection mode of operation.
 19. The interface device according to claim 16, wherein said substrate is selected from a group comprising a semiconductor, silicon on insulator (SOI), insulating substrate replacement, and a bulk substrate having a global depletion layer that isolates top devices from said substrate.
 20. The interface device according to claim 16, wherein said first well is selected from a group consisting of low doped (n−, p−), medium doped (n, p), high doped (n+, p+), and highly doped (n++, p++) said second well is selected from a group consisting of intrinsic undoped, and very low doped (n−−, p−−).
 21. The interface device according to claim 16, wherein said first and second well is at least one of orthogonal with said control gate, and at a specific angle from said control gate.
 22. The interface device according to claim 16, wherein the potential applied to said control gate comprises one or more pulses signal having two or more controlled amplitude levels, controlled time duration, and controlled transition times.
 23. An interface device for interfacing between classic field effect transistor (FET) circuitry and quantum circuitry, comprising: a substrate; a classic FET well constructed on said substrate and operative to be connected to classic FET circuitry to form a classic side; a quantum dot well constructed on said substrate and operative to interface with quantum circuitry to form a quantum side; a control gate constructed over at least a portion of said quantum dot well; wherein a first pulse signal at a first time instance applied to said control gate controls tunneling of a single quantum particle through a local depleted tunnel path from said classic side to said quantum side in an injector mode of operation; and wherein a second pulse signal at a second time instance applied to said control gate allows tunneling of a single quantum particle through a local depleted tunneling path from the said quantum side to said classic side in a detector mode of operation.
 24. The interface device according to claim 23, wherein said classic FET well is selected from a group consisting of low doped (n−, p−), medium doped (n, p), high doped (n+, p+), and highly doped (n++, p++) and said quantum dot well is selected from a group consisting of intrinsic undoped, and very low doped (n−−, p−−).
 25. The interface device according to claim 23, wherein said potential applied to said control gate comprises one or more pulse signals having two or more controlled amplitude levels, controlled time duration, and transition time.
 26. The interface device according to claim 23, wherein a third potential is applied to said classic well in the injector mode of operation.
 27. The interface device according to claim 23, wherein said classic well is left floating to enable said single quantum particle to be detected. 